IDLE_CHK_ERROR
IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR, "QM: QSTATUS_LOW_EXT_A is not 0");
IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR, "QM: QSTATUS_HIGH_EXT_A is not 0");
IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE4 is not 0");
IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE5 is not 0");
IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE6 is not 0");
IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE7 is not 0");
IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd;");
IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_0 register");
IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_1 register");
IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_2 register");
IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_3 register");
IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0), IDLE_CHK_ERROR, "NIG: interrupt 0 is active");
IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_1, ((val & 0x783FF0F) != 0), IDLE_CHK_ERROR, "NIG: interrupt 1 is active");
IDLE_CHK_1(0x2, NIG_REG_NIG_PRTY_STS, ((val & ~0xFFC00000) != 0), IDLE_CHK_ERROR, "NIG: parity interrupt is active");
IDLE_CHK_1(0x1C, NIG_REG_NIG_PRTY_STS_0, ((val & ~0xFFC00000) != 0), IDLE_CHK_ERROR, "NIG: parity 0 interrupt is active");
IDLE_CHK_1(0x4, NIG_REG_NIG_PRTY_STS_1, ((val & 0xff) != 0), IDLE_CHK_ERROR, "NIG: parity 1 interrupt is active");
IDLE_CHK_1(0x18, NIG_REG_NIG_PRTY_STS_1, (val != 0), IDLE_CHK_ERROR, "NIG: parity 1 interrupt is active");
IDLE_CHK_1(0x1F, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "TSEM: interrupt 1 is active");
IDLE_CHK_1(0x1F, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "CSEM: interrupt 1 is active");
IDLE_CHK_1(0x1F, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "USEM: interrupt 1 is active");
IDLE_CHK_1(0x1F, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "XSEM: interrupt 1 is active");
IDLE_CHK_1(0x1F, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "TSDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "TSDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "CSDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "CSDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "USDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "USDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "XSDM: interrupt 0 is active");
IDLE_CHK_1(0x1F, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "XSDM: interrupt 0 is active");
IDLE_CHK_1(0x1C, QM_REG_VOQCRDERRREG, ((val & 0xFFFF) != 0), IDLE_CHK_ERROR, "QM: VOQ credit error register is not 0 (VOQ credit overflow/underflow)");
IDLE_CHK_1(0x1C, QM_REG_BYTECRDERRREG, ((val & 0xFFF) != 0), IDLE_CHK_ERROR, "QM: Byte credit error register is not 0 (Byte credit overflow/underflow)");
IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_0).");
IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_0).");
IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_1).");
IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_1).");
IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (MCP).");
IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (MCP).");
IDLE_CHK_1(0x1C, IGU_REG_SILENT_DROP, (val != 0), IDLE_CHK_ERROR, "Some messages were not executed in the IGU.");
IDLE_CHK_1(0x1C, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x2D), IDLE_CHK_ERROR, "PXP2: rq_read_credit and rq_write_credit are not 5");
IDLE_CHK_1(0x10, QM_REG_FWVOQ0TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq0 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ1TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq1 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ2TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq2 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ3TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq3 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ4TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq4 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ5TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq5 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ6TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq6 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x10, QM_REG_FWVOQ7TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq7 is mapped to HwVoq7 (non-TX HwVoq)");
IDLE_CHK_1(0x3, 0x2114, ((val & 0x0FF010) != 0), IDLE_CHK_ERROR, "PCIE: ucorr_err_status is not 0");
IDLE_CHK_1(0x3, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40100");
IDLE_CHK_1(0x2, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40040100");
IDLE_CHK_1(0x2, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40040100");
IDLE_CHK_1(0x1C, 0x2104, ((val & 0x0FD010) != 0), IDLE_CHK_ERROR, "PCIE: ucorr_err_status is not 0");
IDLE_CHK_1(0x1C, 0x2814, ((val & ~0x2040902) != 0), IDLE_CHK_ERROR, "PCIE: Func 0 1: attentions register is not 0x2040902");
IDLE_CHK_1(0x1C, 0x2854, ((val & ~0x10240902) != 0), IDLE_CHK_ERROR, "PCIE: Func 2 3 4: attentions register is not 0x10240902");
IDLE_CHK_1(0x1C, 0x285c, ((val & ~0x10240902) != 0), IDLE_CHK_ERROR, "PCIE: Func 5 6 7: attentions register is not 0x10240902");
IDLE_CHK_1(0x18, 0x3040, ((val & 0x2) != 0), IDLE_CHK_ERROR, "PCIE: Overflow in DLP2TLP buffer");
IDLE_CHK_1(0x1C, PGLUE_B_REG_INCORRECT_RCV_DETAILS, (val != 0), IDLE_CHK_ERROR, "PGLUE_B: Packet received from PCIe not according to the rules.");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rq_rbc_done is not 1");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rq_cfg_done is not 1");
IDLE_CHK_1(0x1F, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR, "PXP2: rd_start_init is not 1");
IDLE_CHK_1(0x1F, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rd_init_done is not 1");
IDLE_CHK_1(0x1F, PXP2_REG_RD_DISABLE_INPUTS , (val != 0), IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled");
IDLE_CHK_1(0x3, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0), IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0");
IDLE_CHK_1(0x3, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR, "PXP2: pgl_read_blocked is not 0");
IDLE_CHK_1(0x1F, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR, "CFC: error vector is not 0");
IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0), IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0");
IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR, "CFC: number of alloc LCIDs is not 0");
IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR, "CFC: number of leaving LCIDs is not 0");
IDLE_CHK_1(0x1F, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR, "CFC: Interrupt status is not 0");
IDLE_CHK_1(0x1F, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR, "CDU: Interrupt status is not 0");
IDLE_CHK_1(0x1F, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "CCM: Interrupt status is not 0");
IDLE_CHK_1(0x1F, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TCM: Interrupt status is not 0");
IDLE_CHK_1(0x1F, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "UCM: Interrupt status is not 0");
IDLE_CHK_1(0x1F, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "XCM: Interrupt status is not 0");
IDLE_CHK_1(0xF, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR, "PBF: Interrupt status is not 0");
IDLE_CHK_1(0x1F, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TIMERS: Interrupt status is not 0");
IDLE_CHK_1(0x1F, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR, "DORQ: Interrupt status is not 0");
IDLE_CHK_1(0x1F, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR, "SRCH: Interrupt status is not 0");
IDLE_CHK_1(0x1F, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR, "PRS: Interrupt status is not 0");
IDLE_CHK_1(0x1F, BRB1_REG_BRB1_INT_STS, ((val & ~0xFC00) != 0), IDLE_CHK_ERROR, "BRB1: Interrupt status is not 0");
IDLE_CHK_1(0x1F, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0), IDLE_CHK_ERROR, "XPB: Interrupt status is not 0");
IDLE_CHK_1(0x1F, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0), IDLE_CHK_ERROR, "UPB: Interrupt status is not 0");
IDLE_CHK_1(0x1F, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR, "QM: Interrupt status is not 0");
IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR, "QM: Credit error register is not 0 (byte or credit overflow/underflow)");
IDLE_CHK_1(0x1F, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR, "DORQ: DORQ queue is full");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_3 is not 0");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_4 is not 0");
IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0");
IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_3 is not 0");
IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_4 is not 0");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_3_MCP, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_3 is not 0");
IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_4 is not 0");
IDLE_CHK_1(0x1F, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR, "CDU: ERROR_DATA is not 0");
IDLE_CHK_1(0x1F, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: STORM declared message length unequal to actual");
IDLE_CHK_1(0x1F, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: CSDM declared message length unequal to actual");
IDLE_CHK_1(0x1F, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: TSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: XSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: USEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: PBF declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: STORM declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: TSDM declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: PRS declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: PBF declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: USEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: CSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: STORM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: USDM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: TSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: CSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: XSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: DORQ declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: STORM declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: XSDM declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: TSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: CSEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: USEM declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: DORQ declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: PBF declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: NIG0 declared message length unequal to actual");
IDLE_CHK_1(0x1F, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: NIG1 declared message length unequal to actual");
IDLE_CHK_1(0x1F, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR, "QM: OVFQNUM is not 0");
IDLE_CHK_1(0x1F, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR, "QM: OVFERROR is not 0");
case IDLE_CHK_ERROR: \