ARRSIZE
for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
#ifndef ARRSIZE
for (i = 0; i < ARRSIZE(cid_resc->cookies); i++)
ASSERT_STATIC( ARRSIZE(context->proto_start) == ARRSIZE(context->proto_end) );
for (i = 0; i < ARRSIZE(context->proto_start); i++ )
ERR_IF(type >= ARRSIZE(pdev->context_info->proto_pending)) )
DbgBreakIf(type >= ARRSIZE(pdev->context_info->proto_pending)) ;
ERR_IF(type >= ARRSIZE(pdev->context_info->proto_end)) ||
DbgBreakIf(type >= ARRSIZE(pdev->context_info->proto_end));
if ERR_IF(type >= ARRSIZE(pdev->context_info->proto_pending))
DbgBreakIf(type >= ARRSIZE(pdev->context_info->proto_pending)) ;
for(i=0 ; i < ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority) ; i++)
if(i == ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority))
for(i=0 ; i < ARRSIZE(pg) ; i++)
u8_t num_of_pri = ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority);
for(i=0; i < ARRSIZE(cos_data.entry_data) ; i++)
ARRSIZE(pg_pri_orginal_spread),
ASSERT_STATIC(DCBX_MAX_NUM_PRI_PG_ENTRIES == ARRSIZE(ieee_ets->priority_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tc_bw_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tsa_assignment_table));
for (pri = (ARRSIZE(ieee_ets->priority_assignment_table) -1);
for (pri = 0; pri < ARRSIZE(ieee_ets->priority_assignment_table); pri++)
DbgBreakIf(ARRSIZE(ets_drv_param->cos_params) <= cos_entry);
ASSERT_STATIC( MAX_PFC_PRIORITIES == ARRSIZE(pdev->dcbx_info.pri_to_cos));
for( pri = 0; pri < ARRSIZE(pdev->dcbx_info.pri_to_cos) ; pri++)
for (pri = 0; pri < ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority); pri++)
for (i = 0; i < ARRSIZE(pdev->params.dcbx_port_params.ets.cos_params); i++) {
const u8_t invalid_tc = ARRSIZE(ieee_ets->priority_assignment_table);
pri < ARRSIZE(ieee_ets->priority_assignment_table);
pri_remap < ARRSIZE(ieee_ets->priority_assignment_table);
for( index=0 ; index < ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority) ;index++)
ARRSIZE(app->app_pri_tbl),
index < ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority) ;
for (pri = 0; pri < ARRSIZE(pfc_fw_cfg->traffic_type_to_priority_cos) ; pri++)
for (pri = 0; pri < ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority); pri++)
ARRSIZE(local_mib_ext->app_pri_tbl_ext),
ASSERT_STATIC(ARRSIZE(lldp_params->remote_chassis_id) >= ARRSIZE(mcp_lldp_params.peer_chassis_id));
for(i=0 ; i< ARRSIZE(mcp_lldp_params.peer_chassis_id) ; i++)
ASSERT_STATIC(ARRSIZE(lldp_params->remote_port_id) > ARRSIZE(mcp_lldp_params.peer_port_id));
for(i=0 ; i<ARRSIZE(mcp_lldp_params.peer_port_id) ; i++)
ASSERT_STATIC(ARRSIZE(lldp_params->local_chassis_id) >= ARRSIZE(mcp_dcbx_stat.local_chassis_id));
for(i=0 ; i< ARRSIZE(mcp_dcbx_stat.local_chassis_id) ; i++)
ASSERT_STATIC(ARRSIZE(lldp_params->local_port_id) >= ARRSIZE(mcp_dcbx_stat.local_port_id));
for(i=0 ; i< ARRSIZE(mcp_dcbx_stat.local_port_id) ; i++)
ARRSIZE(dcbx_params->config_dcbx_params.admin_configuration_bw_percentage),
ARRSIZE(dcbx_params->config_dcbx_params.admin_configuration_ets_pg),
ARRSIZE(dcbx_params->config_dcbx_params.admin_priority_app_table),
ARRSIZE(admin_mib.features.app.app_pri_tbl));
ARRSIZE(dcbx_params->local_configuration_bw_percentage),
ARRSIZE(dcbx_params->local_configuration_ets_pg),
ARRSIZE(dcbx_params->local_priority_app_table),
ARRSIZE(local_mib.features.app.app_pri_tbl));
ARRSIZE(dcbx_params->remote_configuration_bw_percentage),
ARRSIZE(dcbx_params->remote_configuration_ets_pg),
ARRSIZE(dcbx_params->remote_priority_app_table),
ARRSIZE(remote_mib.features.app.app_pri_tbl));
for(entry = 0; entry < ARRSIZE(app->app_pri_tbl); entry++)
if(ARRSIZE(app->app_pri_tbl) <= (*next_free_app_id_entry) )
if (ARRSIZE(app->app_pri_tbl) <= traf_type_entry)
DbgBreakIf(ARRSIZE(app->app_pri_tbl) <= (*next_free_app_id_entry));
DbgBreakIf(ARRSIZE(app->app_pri_tbl) <= traf_type_entry );
ASSERT_STATIC(ARRSIZE(os_ets_params->priority_assignment_table) ==
ASSERT_STATIC(ARRSIZE(os_ets_params->tc_bw_assignment_table) ==
ASSERT_STATIC(ARRSIZE(os_ets_params->tsa_assignment_table) ==
pri < ARRSIZE(os_ets_params->priority_assignment_table);
ARRSIZE(pg_bw_tbl) ,
ARRSIZE(pri_pg));
ARRSIZE(pdev->params.dcbx_config_params.admin_configuration_bw_percentage) ,
ARRSIZE(pdev->params.dcbx_config_params.admin_configuration_ets_pg));
for(i = 0; i<ARRSIZE(pdev->params.dcbx_config_params.admin_priority_app_table); i++)
for(i = 0; i < ARRSIZE(ets_params->priority_assignment_table); i++)
ASSERT_STATIC(DCBX_MAX_NUM_PRI_PG_ENTRIES == ARRSIZE(ieee_ets->priority_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tc_bw_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tsa_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PRI_PG_ENTRIES == ARRSIZE(ieee_ets->priority_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tc_bw_assignment_table));
ASSERT_STATIC(DCBX_MAX_NUM_PG_BW_ENTRIES == ARRSIZE(ieee_ets->tsa_assignment_table));
for(i = 0; i < ARRSIZE(ieee_ets->priority_assignment_table) ; i++)
ARRSIZE(cee_classif->app_pri_tbl),
ARRSIZE(p_local_mib_ext->app_pri_tbl_ext),
for (i = 0; i < ARRSIZE(pg_help_data->pg_entry_data); i++)
for (add_traf_type = 0; add_traf_type < ARRSIZE(pg_help_data->pg_entry_data); add_traf_type++)
ASSERT_STATIC(ARRSIZE(pg_help_data->pg_entry_data) ==
ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority));
for (search_traf_type = 0; search_traf_type < ARRSIZE(pg_help_data->pg_entry_data); search_traf_type++)
for(i=0; i < ARRSIZE(ets->cos_params) ; i++)
const u8_t num_of_pri = ARRSIZE(pdev->params.dcbx_port_params.app.traffic_type_priority);
(ARRSIZE(pg_help_data->pg_entry_data) <= pg_help_data->num_of_pg)||
ASSERT_STATIC( ARRSIZE(mf_info->min_bw) == ARRSIZE(mf_info->max_bw) )
for (i = 0; i < ARRSIZE(mf_info->min_bw); i++)
for (i = 0; i < ARRSIZE(pdev->params.l2_cli_con_params); i++)
ASSERT_STATIC( ARRSIZE(pdev->params.l2_rx_desc_cnt) == ARRSIZE(pdev->params.mtu));
if( lm_cli_idx >= ARRSIZE(pdev->params.l2_rx_desc_cnt))
for (index = 0; index < ARRSIZE(pdev->lm_cli_drv_ver_to_shmem.cli_drv_ver.versions); index++)
for (i = 0; i < ARRSIZE(pdev->hw_info.mem_base); i++)
ASSERT_STATIC(LM_DMAE_MAX_TYPE == ARRSIZE(pdev->dmae_info.ctx_arr));
if (new_sge_idx >= ARRSIZE(operation->blocks))
for (vnic = 0; vnic < ARRSIZE(ram_data.vnic.vnic_max_rate); vnic++)
u8_t* ptr_arr[ARRSIZE(eeprom_data)] = {0}; // for convinence of coding
for( idx = 0; idx < ARRSIZE(eeprom_data) ; idx++ )
REG_WR_DMAE_LEN(pdev, reg_offset, wb_data, ARRSIZE(wb_data));
DbgBreakIf(func >= ARRSIZE(lm_hw_lock_table));
DbgBreakIf(func >= ARRSIZE(lm_hw_lock_table));
DbgBreakIf(func >= ARRSIZE(lm_hw_lock_table));
for (vnic = 0; vnic < ARRSIZE(ram_data.vnic.vnic_min_rate); vnic++)
mm_memcpy(entry->addr, addr, ARRSIZE(entry->addr));
for (i=0; i<ARRSIZE(nig_mirror->entries); ++i)
for (i=0; i<ARRSIZE(nig_mirror->entries); ++i)
(mm_memcmp(cur_entry->addr, addr, ARRSIZE(cur_entry->addr))) )
for (i = 0; i < ARRSIZE(mcp_vf_disabled); i++)
for (i = 0; i < ARRSIZE(mcp_vf_disabled) ; i++)
DbgBreakIf( pdev->vars.num_attn_sig_regs > ARRSIZE(pdev->vars.attn_sig_af_inv_reg_addr) );
lm_read_attn_regs(pdev, attn_sig_af_inv_arr, ARRSIZE(attn_sig_af_inv_arr));
if (lm_recoverable_error(pdev, attn_sig_af_inv_arr,ARRSIZE(attn_sig_af_inv_arr)))
for (index = 0; index < ARRSIZE(pdev->vars.attn_groups_output); index++)
for (i = 0; i < ARRSIZE(group_mask_arr); i++)
DbgBreakIf( chip_idx >= ARRSIZE( init_mask_values_arr[0].mask_value ) );
for( mask_idx = 0; mask_idx < ARRSIZE(init_mask_values_arr); mask_idx++ )
ASSERT_STATIC(ARRSIZE(debug_info->attn_sig) >= MAX_ATTN_REGS);
u32_t non_split_vals[ARRSIZE(non_split_offsets)] = {0};
static u32_t reg_nig_port_restore[MAX_FUNC_NUM][ARRSIZE(reg_offsets_port0)] = {{0}};
ASSERT_STATIC( ARRSIZE(reg_nig_port_restore[0]) == ARRSIZE(reg_offsets_port0) );
ASSERT_STATIC( ARRSIZE(reg_nig_port_restore[1]) == ARRSIZE(reg_offsets_port1) );
ARRSIZE(reg_nig_port_restore[idx]),
ARRSIZE(reg_nig_port_restore_wb[idx]) );
for( idx = 0; idx < ARRSIZE(non_split_vals); idx++ )
for( idx = 0; idx < ARRSIZE(non_split_vals); idx++ )
lm_read_attn_regs(pdev, attn_sig_af_inv_arr, ARRSIZE(attn_sig_af_inv_arr));
return lm_recoverable_error(pdev, attn_sig_af_inv_arr, ARRSIZE(attn_sig_af_inv_arr));
num_dwords = ARRSIZE(ver_str)/sizeof(u32_t);
ver_str_end = ver_str + ARRSIZE(ver_str) - 1;
ASSERT_STATIC( 3 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[0].threshold) ) ;
ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout0) ) ;
ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout1) ) ;
ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout2) ) ;
ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout3) ) ;
#define LM_GRC_TIMEOUT_MAX_IGNORE ARRSIZE(g_lm_chip_global[0].grc_timeout_val)
static const u8_t arr_size = ARRSIZE(g_lm_chip_global[0].grc_timeout_val);
static const u32_t ftq_mask = ( 1 << ARRSIZE(reg_arr_ftq) ) - 1 ; // we need all regs to be 1...
u32_t restore_arr[max(ARRSIZE(reg_arr_e1_e2),ARRSIZE(reg_arr_e3))] = {0};
const u8_t idx_max = CHIP_IS_E3(pdev) ? ARRSIZE(reg_arr_e3) : ARRSIZE(reg_arr_e1_e2) ;
for( idx = 0; idx < ARRSIZE(reg_arr_ftq); idx++ )
ASSERT_STATIC( 2 == ARRSIZE(opcode_arr) );
for( opcode_idx = 0; opcode_idx < ARRSIZE(opcode_arr); opcode_idx++ )
if( ERR_IF(PORT_ID(pdev) > 1) || ERR_IF(( FUNC_ID(pdev)) >= ARRSIZE(g_lm_loader.path_arr[PATH_ID(pdev)].func_arr)) )
for (event_idx = 0; event_idx < ARRSIZE(event_functions_arr); ++event_idx)
if (pdev->params.pfunc_abs < ARRSIZE(g_lm_chip_global[0].func_en))
if (pfunc_abs < ARRSIZE(g_lm_chip_global[0].func_en))
ASSERT_STATIC(LM_TPA_MAX_AGG_SIZE == ARRSIZE(cqe->sgl_or_raw_data.sgl));
DbgBreakIf(ARRSIZE(cqe->sgl_or_raw_data.sgl) < sge_num_elem);
DbgBreakIf(ARRSIZE(cqe->sgl_or_raw_data.sgl) <= fw_sge_index);
ERR_IF((ARRSIZE(pdev->params.l2_cli_con_params) <= chain_idx) ||
for (i = 0; i < ARRSIZE(pdev->client_info); i++)
for (i = 0; i < ARRSIZE(pdev->client_info); i++)
ERR_IF((ARRSIZE(pdev->rx_info.rxq_chain) <= cid)))
ERR_IF((ARRSIZE(pdev->rx_info.rxq_chain) <= cid)))
for(i = 0; i < ARRSIZE(tpa_chain->start_coales_bd) ; i++)
for (lm_cli_idx=0; lm_cli_idx < ARRSIZE(pdev->slowpath_info.mcast_obj); lm_cli_idx++)
ASSERT_STATIC(ARRSIZE(slowpath_data->mac_rdata) == ARRSIZE(slowpath_data->rx_mode_rdata));
ASSERT_STATIC(ARRSIZE(slowpath_data->mac_rdata) == ARRSIZE(slowpath_data->mcast_rdata));
for (i = 0; i < ARRSIZE(slowpath_data->mac_rdata); i++ )
ERR_IF((ARRSIZE(pdev->tx_info.chain) <= cid) || !page_cnt))
ERR_IF((ARRSIZE(pdev->rx_info.rxq_chain) <= cid) || !page_cnt))
ERR_IF((ARRSIZE(pdev->rx_info.rcq_chain) <= cid) || !page_cnt))
ERR_IF((ARRSIZE(pdev->rx_info.rxq_chain) <= cid) || !page_cnt))
ERR_IF((ARRSIZE(pdev->tx_info.chain) <= cid)))
if( sb_id >= ARRSIZE(pdev->vars.status_blocks_arr) )
DbgBreakIf( sb_id >= ARRSIZE(pdev->vars.status_blocks_arr) ) ;
ERR_IF((ARRSIZE(pdev->rx_info.rxq_chain) <= cid)))
ERR_IF((ARRSIZE(pdev->rx_info.rcq_chain) <= cid)))
if( sb_id >= ARRSIZE(pdev->vars.status_blocks_arr) )
DbgBreakIf( sb_id >= ARRSIZE(pdev->vars.status_blocks_arr) ) ;
DbgBreakIf(!(pdev && (drv_sb_id <= ARRSIZE(pdev->vars.status_blocks_arr))));
for (obj_idx = 0; obj_idx < ARRSIZE(vlan_mac_objs); obj_idx++)
for (idx = 0; idx < ARRSIZE(mac_types); idx++)
for (i = 0; i < ARRSIZE(params.ind_table); i++)
ERR_IF( type >= ARRSIZE( pdev->cid_recycled_callbacks ) ) ||
DbgBreakIf( type >= ARRSIZE( pdev->cid_recycled_callbacks ) );
ERR_IF( type >= ARRSIZE( pdev->cid_recycled_callbacks ) ) ||
DbgBreakIf( type >= ARRSIZE( pdev->cid_recycled_callbacks ) );
ERR_IF( type >= ARRSIZE( pdev->sq_info.sq_comp_cb ) ) ||
ERR_IF( type >= ARRSIZE( pdev->sq_info.sq_comp_cb ) ) ||
if (client_info_idx >= ARRSIZE(pdev->client_info))
DbgBreakIf(client_info_idx >= ARRSIZE(pdev->client_info));
lm_status = lm_stats_set_dmae_operation_sges(pdev, operation, sges, ARRSIZE(sges));
lm_status = lm_stats_set_dmae_operation_sges(pdev, operation, sges, ARRSIZE(sges));
ASSERT_STATIC(LM_STATS_TOE_IDX<ARRSIZE(stats_fw->fw_stats_req->query));
ASSERT_STATIC(LM_STATS_FCOE_IDX<ARRSIZE(stats_fw->fw_stats_req->query));
ASSERT_STATIC(LM_STATS_FIRST_QUEUE_QUERY_IDX < ARRSIZE(stats_fw->fw_stats_req->query));
arr_cnt = ARRSIZE(pdev->vars.stats.stats_mirror.stats_fw.toe_xstorm_toe.statistics) ;
arr_cnt = ARRSIZE(pdev->vars.stats.stats_mirror.stats_fw.toe_tstorm_toe.statistics) ;
if( client_id >= ARRSIZE(pdev->params.l2_cli_con_params) )
DbgBreakIf( client_id >= ARRSIZE(pdev->params.l2_cli_con_params) );
ASSERT_STATIC( ARRSIZE(reg_start) == ARRSIZE(count_limit) );
for( i = 0; i< ARRSIZE(reg_start) ; i++ )
DbgBreakIf(!(pdev && ARRSIZE(pdev->toe_info.rcqs) > drv_toe_rss_id));
ERR_IF((ARRSIZE(pdev->params.l2_cli_con_params) <= chain_idx) ||
DbgBreakIf(!(pdev && ARRSIZE(pdev->toe_info.rcqs) > drv_toe_rss_id));
ERR_IF((ARRSIZE(pdev->params.l2_cli_con_params) <= chain_idx) ||
DbgBreakIf(!(pdev && ARRSIZE(pdev->toe_info.scqs) > drv_toe_rss_id));
DbgBreakIf(!(pdev && ARRSIZE(pdev->toe_info.scqs) > drv_toe_rss_id));
DbgBreakIf(!(pdev && ARRSIZE(pdev->iscsi_info.run_time.eq_chain) > sb_idx));
DbgBreakIf(!(pdev && ARRSIZE(pdev->fcoe_info.run_time.eq_chain) > sb_idx));
if (CHK_NULL(pdev) || (ARRSIZE(pdev->iscsi_info.run_time.eq_chain) <= sb_idx))
DbgBreakIf(ARRSIZE(pdev->iscsi_info.run_time.eq_chain) <= sb_idx);
if (CHK_NULL(pdev) || (ARRSIZE(pdev->fcoe_info.run_time.eq_chain) <= sb_idx))
DbgBreakIf(ARRSIZE(pdev->fcoe_info.run_time.eq_chain) <= sb_idx);
if(CHK_NULL(pdev) || ERR_IF((ARRSIZE(pdev->iscsi_info.run_time.eq_chain) <= idx)))
if( idx >= ARRSIZE(pdev->vars.status_blocks_arr) )
DbgBreakIf( idx >= ARRSIZE(pdev->vars.status_blocks_arr) );
if(CHK_NULL(pdev) || ERR_IF((ARRSIZE(pdev->fcoe_info.run_time.eq_chain) <= idx)))
if (idx >= ARRSIZE(pdev->vars.status_blocks_arr))
DbgBreakIf( idx >= ARRSIZE(pdev->vars.status_blocks_arr) );
#define REGS_COUNT ARRSIZE(reg_addrs)
#define IDLE_REGS_COUNT ARRSIZE(idle_addrs)
#define SPLIT_REGS_COUNT ARRSIZE(split_reg_addrs)
#define WREGS_COUNT_E1 ARRSIZE(wreg_addrs_e1)
#define WREGS_COUNT_E1H ARRSIZE(wreg_addrs_e1h)
#define WREGS_COUNT_E2 ARRSIZE(wreg_addrs_e2)
#define WREGS_COUNT_E3 ARRSIZE(wreg_addrs_e3)
#define WREGS_COUNT_E3B0 ARRSIZE(wreg_addrs_e3b0)
#define TIMER_REGS_COUNT_E1 ARRSIZE(timer_status_regs_e1)
#define TIMER_REGS_COUNT_E1H ARRSIZE(timer_status_regs_e1h)
#define TIMER_REGS_COUNT_E2 ARRSIZE(timer_status_regs_e2)
#define TIMER_REGS_COUNT_E3 ARRSIZE(timer_status_regs_e3)
#ifndef ARRSIZE /* ! ECORE_UPSTREAM */
#define TIMER_REGS_COUNT_E3B0 ARRSIZE(timer_status_regs_e3b0)
#define NLM_KNCS ARRSIZE(nlm_netconfigs)
ARRSIZE(nlm_svcs),