usr/src/uts/common/io/hxge/hpi_rxdma.c

481

HXGE_REG_WR64(handle, offset, clk_div.value);

usr/src/uts/common/io/hxge/hpi_rxdma.h

120

HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\

usr/src/uts/common/io/hxge/hpi_txdma.c

370

HXGE_REG_WR64(handle, offset, 0);

usr/src/uts/common/io/hxge/hpi_txdma.h

56

HXGE_REG_WR64(handle, \

usr/src/uts/common/io/hxge/hpi_vmac.c

123

HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value);

usr/src/uts/common/io/hxge/hpi_vmac.c

147

HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);

usr/src/uts/common/io/hxge/hpi_vmac.c

240

HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);

usr/src/uts/common/io/hxge/hpi_vmac.c

43

HXGE_REG_WR64(handle, VMAC_RST, reset.value);

usr/src/uts/common/io/hxge/hpi_vmac.c

57

HXGE_REG_WR64(handle, VMAC_RST, reset.value);

usr/src/uts/common/io/hxge/hxge_pfc.h

49

HXGE_REG_WR64((handle), (offset), (value))

usr/src/uts/common/io/hxge/hxge_rxdma.c

3162

HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3169

HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3176

HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3183

HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3189

HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3192

HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3485

HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3760

HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0);

usr/src/uts/common/io/hxge/hxge_txdma.c

2091

HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7);

usr/src/uts/common/io/hxge/hxge_txdma.c

2096

HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_HI, 0x0ULL);

usr/src/uts/common/io/hxge/hxge_txdma.c

2097

HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, 0x0ULL);

usr/src/uts/common/io/hxge/hxge_txdma.c

2100

HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD,

usr/src/uts/common/io/hxge/hxge_txdma.c

2107

HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp);

usr/src/uts/common/io/hxge/hxge_txdma.c

2124

HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp);

usr/src/uts/common/io/hxge/hxge_txdma.c

2172

HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7);

usr/src/uts/common/io/hxge/hxge_txdma.c

2173

HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_MASK, 0x0);

usr/src/uts/common/io/hxge/hxge_txdma.c

2672

HXGE_REG_WR64(handle, TDC_FIFO_ERR_STAT, fifo_stat.value);