usr/src/uts/common/io/hxge/hpi_vir.c

133

HXGE_REG_WR32(handle, offset, (uint32_t)ldf_mask);

usr/src/uts/common/io/hxge/hpi_vir.c

168

HXGE_REG_WR32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), mgm.value);

usr/src/uts/common/io/hxge/hpi_vir.c

195

HXGE_REG_WR32(handle, LD_INTR_TIM_RES, tm.value);

usr/src/uts/common/io/hxge/hpi_vir.c

224

HXGE_REG_WR32(handle, SID + LDG_SID_OFFSET(sid.ldg), sd.value);

usr/src/uts/common/io/hxge/hpi_vir.c

247

HXGE_REG_WR32(handle, DEV_ERR_MASK, dev_mask.value);

usr/src/uts/common/io/hxge/hpi_vir.c

53

HXGE_REG_WR32(handle, LD_GRP_CTRL + LD_NUM_OFFSET(ld), gnum.value);

usr/src/uts/common/io/hxge/hxge_hw.c

241

HXGE_REG_WR32(handle, PEU_INTR_MASK, 0xffffffff);

usr/src/uts/common/io/hxge/hxge_main.c

4459

HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16, data0);

usr/src/uts/common/io/hxge/hxge_main.c

4460

HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 4, data1);

usr/src/uts/common/io/hxge/hxge_main.c

4461

HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 8, data2);

usr/src/uts/common/io/hxge/hxge_main.c

4462

HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 12, 0);

usr/src/uts/common/io/hxge/hxge_main.c

711

HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E);

usr/src/uts/common/io/hxge/hxge_pfc.c

646

HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);

usr/src/uts/common/io/hxge/hxge_rxdma.c

123

HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);

usr/src/uts/common/io/hxge/hxge_rxdma.c

3702

HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);

usr/src/uts/common/io/hxge/hxge_txdma.c

2845

HXGE_REG_WR32(handle, BLOCK_RESET, reset_reg.value);

usr/src/uts/common/io/hxge/hxge_txdma.c

99

HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);

usr/src/uts/common/io/hxge/hxge_virtual.c

655

HXGE_REG_WR32(hxgep->hpi_handle, PEU_INTR_MASK, parity_err_mask.value);