HXGE_REG_RD64
HXGE_REG_RD64(handle, RDC_PREF_PAR_LOG, &pre_log->value);
HXGE_REG_RD64(handle, RDC_SHADOW_PAR_LOG, &sha_log->value);
HXGE_REG_RD64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
HXGE_REG_RD64(handle, \
HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
HXGE_REG_RD64(handle, VMAC_TX_CFG, &cfg.value);
HXGE_REG_RD64((handle), (offset), (val_p))
HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value);
HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp);
HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_CMD,
HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_CMD,
HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_HI, &tmp);
HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, &tmp);
HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp);
HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp);
HXGE_REG_RD64(handle, TDC_FIFO_ERR_STAT, &fifo_stat.value);
HXGE_REG_RD64(handle, VMAC_TX_FRAME_CNT, &tx_frame_cnt.value);
HXGE_REG_RD64(handle, VMAC_TX_BYTE_CNT, &tx_byte_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_FRAME_CNT, &rx_frame_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_BYTE_CNT, &rx_byte_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_DROP_FR_CNT, &rx_drop_fr_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_DROP_BYTE_CNT, &rx_drop_byte_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_CRC_CNT, &rx_crc_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_PAUSE_CNT, &rx_pause_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_BCAST_FR_CNT, &rx_bcast_fr_cnt.value);
HXGE_REG_RD64(handle, VMAC_RX_MCAST_FR_CNT, &rx_mcast_fr_cnt.value);