Get_OpReg
if (!(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET);
if (!(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET);
intr = (Get_OpReg(ehci_status) & Get_OpReg(ehci_interrupt));
(Get_OpReg(ehci_interrupt) & ~EHCI_INTR_ASYNC_ADVANCE));
(void) Get_OpReg(ehci_status);
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]);
port_status = Get_OpReg(ehci_rh_port_status[port]) &
if (Get_OpReg(ehci_config_flag) == 0) {
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port, Get_OpReg(ehci_rh_port_status[port]), on);
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
port_status = Get_OpReg(ehci_rh_port_status[port]) &
Set_OpReg(ehci_interrupt, (Get_OpReg(ehci_interrupt) &
Set_OpReg(ehci_interrupt, (Get_OpReg(ehci_interrupt) &
(((Get_OpReg(ehci_frame_index) & 0x3FFF) ^
ehci_polled_regsp->ehci_command = Get_OpReg(ehci_command);
ehci_polled_regsp->ehci_interrupt = Get_OpReg(ehci_interrupt);
Get_OpReg(ehci_ctrl_segment);
ehci_async_list_addr = Get_OpReg(ehci_async_list_addr);
Get_OpReg(ehci_config_flag);
Get_OpReg(ehci_periodic_list_base);
Set_OpReg(ehci_command, Get_OpReg(ehci_command) &
(Get_OpReg(ehci_command) | EHCI_CMD_PERIODIC_SCHED_ENABLE));
if (Get_OpReg(ehci_command) & EHCI_CMD_PERIODIC_SCHED_ENABLE) {
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | mask));
(void) Get_OpReg(ehci_status);
(qh_addr != Get_OpReg(ehci_async_list_addr))) {
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
(Get_OpReg(ehci_command) | EHCI_CMD_ASYNC_SCHED_ENABLE));
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
(Get_OpReg(ehci_command) | EHCI_CMD_ASYNC_SCHED_ENABLE |
intr = ((Get_OpReg(ehci_status) & Get_OpReg(ehci_interrupt)) &
Set_OpReg(ehci_command, Get_OpReg(ehci_command) &
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) |
while (!((Get_OpReg(ehci_status)) & (EHCI_INTR_USB
intr = (Get_OpReg(ehci_status)) &
Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET);
ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED);
(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) |
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) |
uint32_t cmd_reg = Get_OpReg(ehci_command);
ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN);
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
ehci_save_regs->ehci_command = Get_OpReg(ehci_command);
ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt);
ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment);
ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr);
ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag);
Get_OpReg(ehci_periodic_list_base);
Set_OpReg(ehci_command, Get_OpReg(ehci_command) &
Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET);
Get_OpReg(ehci_async_list_addr))) {
Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) &
(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF;
cmd_reg = Get_OpReg(ehci_command);
Get_OpReg(ehci_async_list_addr))) {
cmd_reg = Get_OpReg(ehci_command);
if (!Get_OpReg(ehci_async_list_addr)) {
Get_OpReg(ehci_async_list_addr))) {
Get_OpReg(ehci_command), Get_OpReg(ehci_status));
Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index));
Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base));
Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag));
Get_OpReg(ehci_rh_port_status[i]));
(qh_addr != Get_OpReg(ehci_async_list_addr))) {
ASSERT(Get_OpReg(hcr_intr_enable) & HCR_INTR_SOF);
(Get_OpReg(hcr_control) & ~(bit)));
Get_OpReg(hcr_revision), Get_OpReg(hcr_control));
Get_OpReg(hcr_cmd_status), Get_OpReg(hcr_intr_enable));
Get_OpReg(hcr_intr_disable), Get_OpReg(hcr_HCCA));
Get_OpReg(hcr_periodic_curr), Get_OpReg(hcr_ctrl_head));
Get_OpReg(hcr_ctrl_curr), Get_OpReg(hcr_bulk_head));
Get_OpReg(hcr_bulk_curr), Get_OpReg(hcr_done_head));
"\thcr_frame_remaining: 0x%x", Get_OpReg(hcr_frame_interval),
Get_OpReg(hcr_frame_remaining));
Get_OpReg(hcr_frame_number), Get_OpReg(hcr_periodic_strt));
Get_OpReg(hcr_transfer_ls), Get_OpReg(hcr_rh_descriptorA));
Get_OpReg(hcr_rh_descriptorB), Get_OpReg(hcr_rh_status));
for (i = 0; i < (Get_OpReg(hcr_rh_descriptorA) & HCR_RHA_NDP); i++) {
Get_OpReg(hcr_rh_portstatus[i]));
(Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE |
Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) &
revision = Get_OpReg(hcr_revision);
ohcip->ohci_frame_interval = Get_OpReg(hcr_frame_interval);
ohci_frame_interval = Get_OpReg(hcr_frame_interval);
ohci_frame_interval = Get_OpReg(hcr_frame_interval);
curr_control = Get_OpReg(hcr_control);
ASSERT((Get_OpReg(hcr_control) &
ASSERT(Get_OpReg(hcr_intr_enable) & HCR_INTR_SOF);
mask = Get_OpReg(hcr_HCCA);
mask = Get_OpReg(hcr_HCCA);
hcr_control_val = Get_OpReg(hcr_control);
hcr_cmd_status_val = Get_OpReg(hcr_cmd_status);
if ((Get_OpReg(hcr_control) & HCR_CONTROL_IR) == 0)
if (Get_OpReg(hcr_control) & HCR_CONTROL_IR) {
(Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE |
Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) &
Set_OpReg(hcr_control, (Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE |
if (Get_OpReg(hcr_ctrl_head)) {
Get_OpReg(hcr_ctrl_head));
Set_ED(ept->hced_next, Get_OpReg(hcr_ctrl_head));
(Get_OpReg(hcr_control) | HCR_CONTROL_CLE));
if (Get_OpReg(hcr_bulk_head)) {
Get_OpReg(hcr_bulk_head));
Set_ED(ept->hced_next, Get_OpReg(hcr_bulk_head));
(Get_OpReg(hcr_control) | HCR_CONTROL_BLE));
(Get_OpReg(hcr_control) | HCR_CONTROL_PLE));
Set_OpReg(hcr_control, (Get_OpReg(hcr_control) |
ASSERT(!(Get_OpReg(hcr_control) & HCR_CONTROL_CLE));
Set_OpReg(hcr_ctrl_curr, Get_OpReg(hcr_ctrl_head));
ASSERT(Get_OpReg(hcr_ctrl_head));
(Get_OpReg(hcr_control) | HCR_CONTROL_CLE));
ASSERT(!(Get_OpReg(hcr_control) & HCR_CONTROL_BLE));
Set_OpReg(hcr_bulk_curr, Get_OpReg(hcr_bulk_head));
ASSERT(Get_OpReg(hcr_bulk_head));
(Get_OpReg(hcr_control) | HCR_CONTROL_BLE));
(Get_OpReg(hcr_control) & ~(HCR_CONTROL_IE)));
(Get_OpReg(hcr_control) & ~(HCR_CONTROL_PLE)));
(Get_OpReg(hcr_intr_status) & Get_OpReg(hcr_intr_enable));
(void) Get_OpReg(hcr_intr_status);
ohci_save_regs->hcr_control = Get_OpReg(hcr_control);
ohci_save_regs->hcr_cmd_status = Get_OpReg(hcr_cmd_status);
ohci_save_regs->hcr_intr_enable = Get_OpReg(hcr_intr_enable);
ohci_save_regs->hcr_periodic_strt = Get_OpReg(hcr_periodic_strt);
ohci_save_regs->hcr_frame_interval = Get_OpReg(hcr_frame_interval);
ohci_save_regs->hcr_HCCA = Get_OpReg(hcr_HCCA);
ohci_save_regs->hcr_bulk_head = Get_OpReg(hcr_bulk_head);
ohci_save_regs->hcr_ctrl_head = Get_OpReg(hcr_ctrl_head);
Set_OpReg(hcr_control, (Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE |
(Get_OpReg(hcr_done_head) & HCCA_DONE_HEAD_MASK);
Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) &
Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) &
port_status = Get_OpReg(hcr_rh_portstatus[port]);
new_port_status = Get_OpReg(hcr_rh_portstatus[port]);
hub_status = Get_OpReg(hcr_rh_status);
des_A = ohcip->ohci_root_hub.rh_des_A = Get_OpReg(hcr_rh_descriptorA);
des_B = ohcip->ohci_root_hub.rh_des_B = Get_OpReg(hcr_rh_descriptorB);
new_root_hub_status = Get_OpReg(hcr_rh_status);
ohcip->ohci_root_hub.rh_status = Get_OpReg(hcr_rh_status);
new_root_hub_status = Get_OpReg(hcr_rh_status);
new_port_status = Get_OpReg(hcr_rh_portstatus[i]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port, Get_OpReg(hcr_rh_portstatus[port]), on);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
port_status = Get_OpReg(hcr_rh_portstatus[port]);
((Get_OpReg(hcr_intr_status) &
Get_OpReg(hcr_intr_enable)) & HCR_INTR_SOF);
((Get_OpReg(hcr_intr_status) &
Get_OpReg(hcr_intr_enable)) & HCR_INTR_SOF);
ohci_polled_regsp->hcr_done_head = Get_OpReg(hcr_done_head);
(Get_OpReg(hcr_control) | HCR_CONTROL_PLE));
while (!((Get_OpReg(hcr_intr_status)) & HCR_INTR_SOF)) {
if (Get_OpReg(hcr_control) & HCR_CONTROL_PLE) {
(Get_OpReg(hcr_control) & ~HCR_CONTROL_PLE));
while (!((Get_OpReg(hcr_intr_status)) & HCR_INTR_SOF)) {
(uintptr_t)Get_OpReg(hcr_done_head));
control = Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE |
intr = (Get_OpReg(hcr_intr_status) & Get_OpReg(hcr_intr_enable));
(void) Get_OpReg(hcr_intr_status);
intr = (Get_OpReg(hcr_intr_status) & Get_OpReg(hcr_intr_enable));
(Get_OpReg(hcr_control) & (~HCR_CONTROL_PLE)));
(Get_OpReg(hcr_control) | HCR_CONTROL_PLE));
intr = Get_OpReg(hcr_intr_status);
(void) Get_OpReg(hcr_intr_status);
(void) Get_OpReg(hcr_intr_status);
ohci_polled_regsp->hcr_control = Get_OpReg(hcr_control);
ohci_polled_regsp->hcr_cmd_status = Get_OpReg(hcr_cmd_status);
ohci_polled_regsp->hcr_intr_enable = Get_OpReg(hcr_intr_enable);
ohci_polled_regsp->hcr_HCCA = Get_OpReg(hcr_HCCA);
ohci_polled_regsp->hcr_done_head = Get_OpReg(hcr_done_head);
ohci_polled_regsp->hcr_bulk_head = Get_OpReg(hcr_bulk_head);
ohci_polled_regsp->hcr_ctrl_head = Get_OpReg(hcr_ctrl_head);
while (Get_OpReg(addr) != val) { \