FZC_PIO
{"FZC_PIO", FZC_PIO},
#define LDGITMRES (FZC_PIO + 0x00008) /* timer resolution */
#define SID (FZC_PIO + 0x10200) /* 64 LDG, INT data */
#define LDG_NUM (FZC_PIO + 0x20000) /* 69 LDs */
#define MULTI_PART_CTL_REG (FZC_PIO + 0x00000)
#define DMA_BIND_REG (FZC_PIO + 0x10000)
#define LDG_NUM_REG (FZC_PIO + 0x20000)
#define LDGITMRES_REG (FZC_PIO + 0x00008)
#define SID_REG (FZC_PIO + 0x10200)
#define RST_CTL_REG (FZC_PIO + 0x00038)
#define SYS_ERR_MASK_REG (FZC_PIO + 0x00090)
#define SYS_ERR_STAT_REG (FZC_PIO + 0x00098)
#define DIRTY_TID_CTL_REG (FZC_PIO + 0x0010)
#define DIRTY_TID_STAT_REG (FZC_PIO + 0x0018)
#define SMX_CFIG_DAT_REG (FZC_PIO + 0x00040)
#define SMX_INT_STAT_REG (FZC_PIO + 0x00048)
#define SMX_CTL_REG (FZC_PIO + 0x00050)
#define SMX_DBG_VEC_REG (FZC_PIO + 0x00058)
#define PIO_DBG_SEL_REG (FZC_PIO + 0x00060)
#define PIO_TRAIN_VEC_REG (FZC_PIO + 0x00068)
#define PIO_ARB_CTL_REG (FZC_PIO + 0x00070)
#define PIO_ARB_DBG_VEC_REG (FZC_PIO + 0x00078)
#define GPIO_EN_REG (FZC_PIO + 0x00028)
#define GPIO_DATA_IN_REG (FZC_PIO + 0x00030)