FLASH_CONF_ADDR
rval = ql_24xx_read_flash(ha, FLASH_CONF_ADDR | 0x3AB, &fdata);
rval = ql_24xx_read_flash(ha, FLASH_CONF_ADDR | 0x39F,
rval = ql_24xx_read_flash(ha, FLASH_CONF_ADDR |
FLASH_CONF_ADDR | 0x0352,
FLASH_CONF_ADDR | 0x03d8,
if ((addr & FLASH_ADDR_MASK) == FLASH_CONF_ADDR) {
FLASH_CONF_ADDR | 0x105, &fdata);
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x100 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x100 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x300 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x100 |
(void) ql_24xx_write_flash(ha, FLASH_CONF_ADDR | 0x100 |
uint32_t data, cmd = FLASH_CONF_ADDR | FLASH_R_FLAG;
uint32_t cmd = FLASH_CONF_ADDR;
uint32_t data, cmd = FLASH_CONF_ADDR;
if ((addr & FLASH_ADDR_MASK) == FLASH_CONF_ADDR) {
FLASH_CONF_ADDR | 0x100 | qlge->fdesc.write_statusreg_cmd,
(void) ql_write_flash(qlge, FLASH_CONF_ADDR |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x300 |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
(void) ql_write_flash(qlge, FLASH_CONF_ADDR | 0x330 |
FLASH_CONF_ADDR | 0x101, 0x80);
FLASH_CONF_ADDR | 0x100 | qlge->fdesc.write_statusreg_cmd,
FLASH_CONF_ADDR | 0x0300 | qlge->fdesc.erase_cmd,
rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x300 | FLASH_RES_CMD,
rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x0400 | FLASH_RDID_CMD,