usr/src/uts/common/io/iwh/iwh_hw.h

350

#define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1)

usr/src/uts/common/io/iwh/iwh_hw.h

351

#define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004)

usr/src/uts/common/io/iwh/iwh_hw.h

352

#define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008)

usr/src/uts/common/io/iwh/iwh_hw.h

353

#define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C)

usr/src/uts/common/io/iwk/iwk_hw.h

349

#define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1)

usr/src/uts/common/io/iwk/iwk_hw.h

350

#define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004)

usr/src/uts/common/io/iwk/iwk_hw.h

351

#define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008)

usr/src/uts/common/io/iwk/iwk_hw.h

352

#define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C)

usr/src/uts/common/io/iwp/iwp_hw.h

347

#define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1)

usr/src/uts/common/io/iwp/iwp_hw.h

348

#define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004)

usr/src/uts/common/io/iwp/iwp_hw.h

349

#define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008)

usr/src/uts/common/io/iwp/iwp_hw.h

350

#define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C)