usr/src/uts/intel/io/fdc.c

1903

save = inb(fcp->c_regbase + FCR_SRA);

usr/src/uts/intel/io/fdc.c

1907

outb(fcp->c_regbase + FCR_SRA, enable_code);

usr/src/uts/intel/io/fdc.c

1908

outb(fcp->c_regbase + FCR_SRA, enable_code);

usr/src/uts/intel/io/fdc.c

1911

outb(fcp->c_regbase + FCR_SRA, FSA_CR5);

usr/src/uts/intel/io/fdc.c

1917

outb(fcp->c_regbase + FCR_SRA, FSA_DISB);

usr/src/uts/intel/io/fdc.c

1919

outb(fcp->c_regbase + FCR_SRA, save);

usr/src/uts/intel/io/fdc.c

777

save = inb(fcp->c_regbase + FCR_SRA);

usr/src/uts/intel/io/fdc.c

784

outb(fcp->c_regbase + FCR_SRA, FSA_ENA5);

usr/src/uts/intel/io/fdc.c

785

outb(fcp->c_regbase + FCR_SRA, FSA_ENA5);

usr/src/uts/intel/io/fdc.c

788

outb(fcp->c_regbase + FCR_SRA, 0x0F);

usr/src/uts/intel/io/fdc.c

792

outb(fcp->c_regbase + FCR_SRA, 0x0D);

usr/src/uts/intel/io/fdc.c

796

outb(fcp->c_regbase + FCR_SRA, 0x0E);

usr/src/uts/intel/io/fdc.c

807

outb(fcp->c_regbase + FCR_SRA, FSA_DISB);

usr/src/uts/intel/io/fdc.c

812

outb(fcp->c_regbase + FCR_SRA, FSA_ENA6);

usr/src/uts/intel/io/fdc.c

813

outb(fcp->c_regbase + FCR_SRA, FSA_ENA6);

usr/src/uts/intel/io/fdc.c

816

outb(fcp->c_regbase + FCR_SRA, 0x0F);

usr/src/uts/intel/io/fdc.c

820

outb(fcp->c_regbase + FCR_SRA, 0x0D);

usr/src/uts/intel/io/fdc.c

824

outb(fcp->c_regbase + FCR_SRA, 0x0E);

usr/src/uts/intel/io/fdc.c

835

outb(fcp->c_regbase + FCR_SRA, FSA_DISB);

usr/src/uts/intel/io/fdc.c

838

outb(fcp->c_regbase + FCR_SRA, save);