AMD_IOMMU_REG_GET32
ASSERT(AMD_IOMMU_REG_GET32(&ivrsp->ivrs_ivinfo,
ASSERT(AMD_IOMMU_REG_GET32(&ivrsp->ivrs_ivinfo,
AMD_IOMMU_REG_GET32(&ivrs_ivinfo, AMD_IOMMU_ACPI_HT_ATSRSV);
AMD_IOMMU_REG_GET32(&ivrs_ivinfo, AMD_IOMMU_ACPI_VA_SIZE);
AMD_IOMMU_REG_GET32(&ivrs_ivinfo, AMD_IOMMU_ACPI_PA_SIZE);
iommu->aiomt_rng_valid = AMD_IOMMU_REG_GET32(&range,
iommu->aiomt_rng_bus = AMD_IOMMU_REG_GET32(&range,
iommu->aiomt_first_devfn = AMD_IOMMU_REG_GET32(&range,
iommu->aiomt_last_devfn = AMD_IOMMU_REG_GET32(&range,
iommu->aiomt_ht_unitid = AMD_IOMMU_REG_GET32(&range,
iommu->aiomt_htatsresv = AMD_IOMMU_REG_GET32(&misc,
iommu->aiomt_vasize = AMD_IOMMU_REG_GET32(&misc,
iommu->aiomt_pasize = AMD_IOMMU_REG_GET32(&misc,
AMD_IOMMU_REG_GET32(&misc, AMD_IOMMU_MSINUM);
cap_type = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_TYPE);
cap_id = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_ID);
iommu->aiomt_npcache = AMD_IOMMU_REG_GET32(&caphdr,
iommu->aiomt_httun = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_HTTUN);
AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_IOTLB);
iommu->aiomt_captype = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_TYPE);
iommu->aiomt_capid = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_ID);
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
TR = AMD_IOMMU_REG_GET32(&event[1],
RZ = AMD_IOMMU_REG_GET32(&event[1],
RW = AMD_IOMMU_REG_GET32(&event[1],
I = AMD_IOMMU_REG_GET32(&event[1],
vaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
TR = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_TR);
RZ = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_RZ);
PE = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_PE);
RW = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_RW);
PR = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_PR);
I = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_IO_PGFAULT_INTR);
domainid = AMD_IOMMU_REG_GET32(&event[1],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
type = AMD_IOMMU_REG_GET32(&event[1],
TR = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_DEVTAB_HWERR_TR);
RW = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_DEVTAB_HWERR_RW);
I = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_DEVTAB_HWERR_INTR);
physaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
type = AMD_IOMMU_REG_GET32(&event[1],
TR = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_PGTABLE_HWERR_TR);
RW = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_PGTABLE_HWERR_RW);
I = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_PGTABLE_HWERR_INTR);
domainid = AMD_IOMMU_REG_GET32(&event[1],
physaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
physaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
type = AMD_IOMMU_REG_GET32(&event[1],
physaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
type = AMD_IOMMU_REG_GET32(&event[1],
physaddr_lo = AMD_IOMMU_REG_GET32(&event[2],
ASSERT(AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE) ==
deviceid = AMD_IOMMU_REG_GET32(&event[0],
TR = AMD_IOMMU_REG_GET32(&event[1],
type = AMD_IOMMU_REG_GET32(&event[1],
event_type = AMD_IOMMU_REG_GET32(&event[1], AMD_IOMMU_EVENT_TYPE);