ESR_REG_WR
ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0);
ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
ESR_REG_WR(handle, ESR_0_CONTROL_REG,
ESR_REG_WR(handle,
ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_1);
ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
ESR_REG_WR(handle, ESR_1_CONTROL_REG,
ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
ESR_REG_WR(handle, ESR_RESET_REG, val);
ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
ESR_REG_WR(handle, ESR_0_CONTROL_REG, ESR_CTL_1G_SERDES);
ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG,
ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
ESR_REG_WR(handle, ESR_RESET_REG, val);
ESR_REG_WR(handle, ESR_RESET_REG, val);
ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
ESR_REG_WR(handle, ESR_1_CONTROL_REG, ESR_CTL_1G_SERDES);
ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
ESR_REG_WR(handle, ESR_RESET_REG, val);
ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0 | ESR_RESET_1);
ESR_REG_WR(handle, ESR_CONFIG_REG, 0);