EDX
ucp->uc_mcontext.gregs[EDX] = (int) sc.sc_edx;
sc.sc_edx = (int) ucp->uc_mcontext.gregs[EDX];
grs[ES], grs[EDX], grs[EDX]);
{ "edx", EDX, MDB_TGT_R_EXPORT },
{ "dx", EDX, MDB_TGT_R_EXPORT | MDB_TGT_R_16 },
{ "dh", EDX, MDB_TGT_R_EXPORT | MDB_TGT_R_8H },
{ "dl", EDX, MDB_TGT_R_EXPORT | MDB_TGT_R_8L },
dst[EDX] = src[REG_RDX];
disp_reg_line(ph, &pstatus, "ebx", EBX, "edx", EDX);
ps->pr_lwp.pr_reg[EDX] = cp->user.u_reg[EDX];
ps->pr_lwp.pr_reg[EDX] = cp->user.u_reg[EDX];
cp->user.u_reg[EDX] = ps->pr_lwp.pr_reg[EDX];
ucp->uc_mcontext.gregs[EDX] = edx;
dst[REG_RDX] = (uint32_t)src[EDX];
dst[REG_RDX] = (uint32_t)src[EDX];
dst[EDX] = src[REG_RDX];
lwp->lwp_status.pr_reg[EDX] = prs32->pr_reg.lxr_dx;
#define R_RVAL2 EDX /* 32 more bits for a 64-bit return value */
EAX, EDX, ECX, EBX, ESI, EDI, EBP, ESP, // 32-bit
REGINFO( DL, "%dl", DX, EDX, EAX_EDX),
REGINFO( DH, "%dh", DX, EDX, EAX_EDX),
REGINFO( DX, "%dx", DL, DH, EDX, EAX_EDX),
REGINFO(EDX, "%edx", DL, DH, DX, EAX_EDX),
REGINFO(EAX_EDX, "%eax:%edx", AL, AH, AX, EAX, DL, DH, DX, EDX),
REGSTORAGE(EAX), REGSTORAGE(EDX), REGSTORAGE(ECX), REGSTORAGE(EBX),
#define REG_EDX (&hardreg_storage_table[EDX])
static struct regclass regclass_32 = { "32-bit", { EAX, EDX, ECX, EBX, ESI, EDI, EBP }};
static struct regclass regclass_32_8 = { "32-bit bytes", { EAX, EDX, ECX, EBX }};
sc.sc_r1 = (int)ucp->uc_mcontext.gregs[EDX];
ucp->uc_mcontext.gregs[EDX] = (int)sc.sc_r1;
dst[REG_RDX] = (uint32_t)src[EDX];
grp[EDX] = (greg32_t)rp->r_rdx;
dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
#define R_R1 EDX
#define REG_R1 EDX