DbgMessage1
DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val);
DbgMessage1(pdev, INFORM, "Reset done, idx = %d\n", idx);
DbgMessage1(pdev, VERBOSE, "%02x: ", j);
DbgMessage1(pdev, VERBOSE, "%02x ", val);
DbgMessage1(pdev, INFORMi, "vid 0x%x\n", pdev->hw_info.vid);
DbgMessage1(pdev, INFORMi, "did 0x%x\n", pdev->hw_info.did);
DbgMessage1(pdev, INFORMi, "svid 0x%x\n", pdev->hw_info.svid);
DbgMessage1(pdev, INFORMi, "ssid 0x%x\n", pdev->hw_info.ssid);
DbgMessage1(pdev, INFORMi, "IRQ 0x%x\n", pdev->hw_info.irq);
DbgMessage1(pdev, INFORMi, "Int pin 0x%x\n", pdev->hw_info.int_pin);
DbgMessage1(pdev, INFORMi, "Cache line size 0x%x\n", (u8_t) val);
DbgMessage1(pdev, INFORMi, "Latency timer 0x%x\n", (u8_t) (val >> 8));
DbgMessage1(pdev, INFORMi, "Revision id 0x%x\n", pdev->hw_info.rev_id);
DbgMessage1(pdev, INFORMi, "Mem base low 0x%x\n", pdev->hw_info.mem_base.as_u32.low);
DbgMessage1(pdev, INFORMi, "Mem base high 0x%x\n",
DbgMessage1(pdev, INFORM, "bar_size 0x%x\n", pdev->hw_info.bar_size);
DbgMessage1(pdev, INFORMi, "Mapped base %p\n", pdev->vars.regview);
DbgMessage1(pdev, INFORMi, "chip id 0x%x\n", pdev->hw_info.chip_id);
DbgMessage1(pdev, INFORMi, "dbg_sb_dpc(): handling RSS status block #%d\n", rss_id);
DbgMessage1(pdev, INFORMi, "dbg_assert_attn_lines() inside! lines_to_assert:0x%x\n", lines_to_assert);
DbgMessage1(pdev, INFORMi, "dbg_isr(): intr_recognized is:%s\n", intr_recognized ? "TRUE" : "FALSE");
DbgMessage1(pdev, INFORMi, "dbg_deassert_attn_lines() inside! lines_to_deassert:0x%x\n", lines_to_deassert);
DbgMessage1(pdev, INFORMi, "dbg_ack_assert_attn_lines() inside! assert_lines_to_ack:0x%x\n", assert_lines_to_ack);
DbgMessage1(pdev, FATAL, "vf ME-REG value: 0x%x\n", val);
DbgMessage1(pdev, FATAL , "### VF lm_common_setup_alloc_resc b_is_alloc=%s\n", b_is_alloc ? "TRUE" : "FALSE" );
DbgMessage1(pdev, FATAL, "lm_alloc_client_info failed lm-status = %d\n", lm_status);
DbgMessage1(pdev, FATAL, "lm_alloc_client_info failed lm-status = %d\n", lm_status);
DbgMessage1(pdev, FATAL, "lm_setup_client_info failed lm-status = %d\n", lm_status);
DbgMessage1(pdev,FATAL,"lm_set_rx_mask(LM_RX_MASK_ACCEPT_NONE) returns %d\n",lm_status);
DbgMessage1(pdev,FATAL,"lm_vf_chip_reset: VF(%d) under reset\n",ABS_VFID(pdev));
DbgMessage1(pdev,FATAL,"lm_vf_chip_reset: recycle resources (including connection) for VF(%d)\n",ABS_VFID(pdev));
DbgMessage1(pdev, FATAL, "vf[%d] is enabled\n", ABS_VFID(pdev));
DbgMessage1(pdev, FATAL, "IGU[%d] is inialized\n", prod_idx);
DbgMessage1(pdev, FATAL, "vf[%d] is not enabled\n", ABS_VFID(pdev));
DbgMessage1(pf_dev,FATAL,"lm_vf_get_free_stats: %d\n",free_st_id);
DbgMessage1(pf_dev,FATAL,"lm_vf_get_free_stats: vnic_per_port is %d)\n",pf_dev->params.vnics_per_port);
DbgMessage1(pf_dev,FATAL,"lm_vf_get_free_cam_offset: %d\n",free_cam_offset);