wrmsr
void wrmsr(u_int msr, uint64_t newval);
void wrmsr(u_int msr, uint64_t newval);
extern void wrmsr(uint32_t, uint64_t *);
if (kmt_rwmsr(addr, &val, wrmsr)) {
void wrmsr(uint32_t, uint64_t);
wrmsr(0x1B, rdmsr(0x1B) & ~APICBASE_ENABLED);
wrmsr(0x1B, rdmsr(0x1B) | APICBASE_ENABLED);
wrmsr(MSR_TSC, TSC_TARGET_WRVAL);
wrmsr(msr, val);
wrmsr(0x10, TSC_TARGET_WRVAL);
wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp);
wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)),
wrmsr(REG_APIC_BASE_MSR, apic_base_msr);
wrmsr(IA32_DEADLINE_TSC_MSR, 1ULL << 63);
wrmsr(IA32_DEADLINE_TSC_MSR, ticks);
wrmsr(IA32_ENERGY_PERF_BIAS_MSR, epb_value);
wrmsr(IA32_CLOCK_MODULATION_MSR, reg);
wrmsr(PWRNOW_PERF_CTL_MSR, reg);
wrmsr(IA32_PERF_CTL_MSR, reg);
wrmsr(IA32_MPERF_MSR, 0);
wrmsr(IA32_APERF_MSR, 0);
wrmsr(IA32_MPERF_MSR, 0);
wrmsr(IA32_APERF_MSR, 0);
wrmsr(MSR_AMD_NB_CFG,
wrmsr(MSR_AMD_NB_CFG, nb_cfg_reg);
wrmsr(MSR_AMD_GSBASE, (uint64_t)cpu);
wrmsr(MSR_AMD_GSBASE, (uint64_t)old);
wrmsr(msr, value);
wrmsr(msr, v);
(void) wrmsr(REG_TSC, 0UL);
(void) wrmsr(MSR_AMD_TSCAUX, 0);
wrmsr(MSR_AMD_DE_CFG,
(void) wrmsr(REG_TSC, 0UL);
(void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
wrmsr(MSR_AMD_STAR,
wrmsr(MSR_AMD_LSTAR,
wrmsr(MSR_AMD_CSTAR,
wrmsr(MSR_AMD_LSTAR,
wrmsr(MSR_AMD_CSTAR,
wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
wrmsr(MSR_INTC_SEP_CS, 0);
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
wrmsr(MSR_AMD_SFMASK, flags);
wrmsr(MSR_INTC_SEP_ESP, 0);
wrmsr(MSR_INTC_SEP_EIP,
wrmsr(MSR_INTC_SEP_EIP,
wrmsr(MSR_AMD_NB_CFG, rdmsr(MSR_AMD_NB_CFG) | AMD_GH_NB_CFG_EN_ECS);
wrmsr(REG_PAT, pat_attr_reg);
wrmsr(cp.cp_ebx, msrval);
wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
wrmsr(MSR_AMD_LSTAR, (uintptr_t)xpv_panic_hypercall);
wrmsr(MSR_AMD_CSTAR, (uintptr_t)xpv_panic_hypercall);
wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]);
wrmsr(MSR_DEBUGCTLMSR, 0);
wrmsr(MSR_DEBUGCTLMSR, gctx->host_debugctl);
wrmsr(MSR_AMD_TSC_RATIO, mult);
wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
wrmsr(MSR_AMD_TSC_RATIO, AMD_TSCM_RESET_VAL);
SDT_PROBE_DEFINE5(vmm, vmx, exit, wrmsr,
wrmsr(MSR_DEBUGCTLMSR, 0);
wrmsr(MSR_DEBUGCTLMSR, vmxctx->host_debugctl);
wrmsr(MSR_LSTAR, guest_msrs[IDX_MSR_LSTAR]);
wrmsr(MSR_CSTAR, guest_msrs[IDX_MSR_CSTAR]);
wrmsr(MSR_STAR, guest_msrs[IDX_MSR_STAR]);
wrmsr(MSR_SF_MASK, guest_msrs[IDX_MSR_SF_MASK]);
wrmsr(MSR_KGSBASE, guest_msrs[IDX_MSR_KGSBASE]);
wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
wrmsr(MSR_IA32_FLUSH_CMD, IA32_FLUSH_CMD_L1D);
wrmsr(MSR_IA32_SPEC_CTRL, val);
wrmsr(MSR_IA32_SPEC_CTRL, val);
wrmsr(MSR_AMD_EFER, val);
wrmsr(MSR_AMD_CPUID7_FEATURES, val);
wrmsr(MSR_IA32_TSX_CTRL, val);
wrmsr(MSR_IA32_TSX_CTRL, val);
wrmsr(MSR_AMD_DE_CFG, val);
wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
wrmsr(MSR_AMD_LSTAR, (uintptr_t)tr_brand_sys_syscall);
wrmsr(MSR_AMD_CSTAR, (uintptr_t)tr_brand_sys_syscall32);
wrmsr(MSR_AMD_LSTAR, (uintptr_t)brand_sys_syscall);
wrmsr(MSR_AMD_CSTAR, (uintptr_t)brand_sys_syscall32);
wrmsr(MSR_INTC_SEP_EIP,
wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)brand_sys_sysenter);
wrmsr(MSR_AMD_LSTAR, (uintptr_t)tr_sys_syscall);
wrmsr(MSR_AMD_CSTAR, (uintptr_t)tr_sys_syscall32);
wrmsr(MSR_AMD_LSTAR, (uintptr_t)sys_syscall);
wrmsr(MSR_AMD_CSTAR, (uintptr_t)sys_syscall32);
wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)tr_sys_sysenter);
wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)sys_sysenter);
wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]);
wrmsr(MSR_AMD_FSBASE, 0x200000000ul);
wrmsr(MSR_AMD_KGSBASE, 0x200000000ul);
wrmsr(MSR_IA32_FEAT_CTRL, fctrl);
wrmsr(MSR_CPC_EXTD_EVTSEL(i),
wrmsr(MSR_CPC_EXTD_EVTSEL(i), evtsel);
wrmsr(MSR_CPC_EXTD_CTR(i), cpc_state->hscs_regs[i].hc_ctr);
wrmsr(MSR_CPC_EXTD_EVTSEL(i), evtsel & ~AMD_PERF_EVTSEL_CTR_EN);
wrmsr(MSR_CPC_EXTD_CTR(i),
wrmsr(MSR_CPC_EXTD_EVTSEL(i),
wrmsr(MSR_AMD_EFER, efer);
wrmsr(MSR_AMD_VM_HSAVE_PA, hsave_pa);
wrmsr(ucode->us_write_msr, (uintptr_t)uusp->ucodep);
wrmsr(MSR_AMD_PATCHLOADER, (uintptr_t)ucodefp);
wrmsr(MSR_INTC_UCODE_REV, 0);
wrmsr(MSR_INTC_UCODE_WRITE, (uintptr_t)uinfop->cui_pending_ucode);
wrmsr(MSR_AMD_GSBASE, kgsbase);
wrmsr(MSR_AMD_KGSBASE, pcb->pcb_gsbase);
wrmsr(MSR_AMD_FSBASE, pcb->pcb_fsbase);
wrmsr(MSR_AMD_GSBASE, kgsbase);
wrmsr((msr), (value)); \
DTRACE_PROBE2(wrmsr, uint64_t, (msr), uint64_t, (value));
wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel);
wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic);
wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel |
wrmsr(opd.opd_pesf(i), 0ULL);
wrmsr(p4_ctrs[i].pc_caddr, cfgs[i]->p4_rawpic);
wrmsr(p4_escrs[cfgs[i]->p4_escr_ndx].pe_addr, escr);
wrmsr(p4_ctrs[i].pc_ctladdr, cccr);
wrmsr(p4_ctrs[i].pc_caddr, cfgs[i]->p4_rawpic);
wrmsr(p4_escrs[cfgs[i]->p4_escr_ndx].pe_addr,
wrmsr(p4_ctrs[i].pc_ctladdr,
wrmsr(p4_ctrs[i].pc_ctladdr, 0ULL);
extern void wrmsr(uint_t, const uint64_t);