writel
(writel((value), ((a)->hw_addr + E1000_##reg))) : \
(writel((value), ((a)->hw_addr + E1000_82542_##reg))))
writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
writel(reg & ~NVREG_ADAPTCTL_RUNNING,
writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
writel(value, base + NvRegMIIData);
writel(reg, base + NvRegMIIControl);
writel(reg | NVREG_ADAPTCTL_RUNNING,
writel(0, base + NvRegReceiverControl);
writel(np->linkspeed, base + NvRegLinkSpeed);
writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
writel(0, base + NvRegReceiverControl);
writel(0, base + NvRegLinkSpeed);
writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
writel(0, base + NvRegTransmitterControl);
writel(0, base + NvRegUnknownTransmitterReg);
writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET,
writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
writel(addr[0], base + NvRegMulticastAddrA);
writel(addr[1], base + NvRegMulticastAddrB);
writel(mask[0], base + NvRegMulticastMaskA);
writel(mask[1], base + NvRegMulticastMaskB);
writel(pff, base + NvRegPacketFilterFlags);
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
writel(0, base + NvRegMulticastAddrB);
writel(0, base + NvRegMulticastMaskA);
writel(0, base + NvRegMulticastMaskB);
writel(0, base + NvRegPacketFilterFlags);
writel(0, base + NvRegAdapterControl);
writel(0, base + NvRegLinkSpeed);
writel(0, base + NvRegUnknownTransmitterReg);
writel(0, base + NvRegUnknownSetupReg6);
writel(mac[0], base + NvRegMacAddrA);
writel(mac[1], base + NvRegMacAddrB);
writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
writel(0, base + NvRegTxRxControl);
writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
writel(0, base + NvRegUnknownSetupReg4);
writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
writel(readl(base + NvRegTransmitterStatus),
writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
writel(readl(base + NvRegReceiverStatus),
writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
writel((np->
writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
writel((u32) virt_to_le32desc(&rx_ring[0]),
writel((u32) virt_to_le32desc(&tx_ring[0]),
writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
writel(NVREG_POWERSTATE_POWEREDUP | i,
writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
writel(0, base + NvRegIrqMask);
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
writel(0, base + NvRegMulticastAddrB);
writel(0, base + NvRegMulticastMaskA);
writel(0, base + NvRegMulticastMaskB);
writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl);
writel(0, base + NvRegIrqMask);
writel(np->orig_mac[0], base + NvRegMacAddrA);
writel(np->orig_mac[1], base + NvRegMacAddrB);
#define __kick_rx() writel(CR_RXE, ns->base + CR)
writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \
writel(readl(ns->base + TXCFG)
writel(readl(ns->base + RXCFG) | RXCFG_RX_FD,
writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT,
writel((readl(ns->base + TXCFG)
writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD,
writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT,
writel(new_cfg, ns->base + CFG);
writel(0, ns->base + RXDP_HI);
writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP);
writel(0x0001, ns->base + CCSR);
writel(0, ns->base + RFCR);
writel(0x7fc00000, ns->base + RFCR);
writel(0xffc00000, ns->base + RFCR);
writel(which, ns->base + CR);
writel(0, ns->base + PQCR);
writel(0, ns->base + TXDP_HI);
writel(i * 2, ns->base + RFCR);
writel(val & ~RFCR_RFEN, rfcr);
writel(val, rfcr);
writel(enable, ns->base + PTSCR);
writel(CR_TXE, ns->base + CR);
writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP);
writel(0, ns->base + IMR);
writel(0, ns->base + IER);
writel(ns->IMR_cache, ns->base + IMR);
writel(0, ns->base + RXDP_HI);
writel(0, ns->base + RXDP);
writel(0, ns->base + IMR);
writel(0, ns->base + IER);
writel(PTSCR_RBIST_RST, ns->base + PTSCR);
writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR);
writel(readl(ns->base + TANAR)
writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
writel(TBICR_MR_AN_ENABLE, ns->base + TBICR);
writel(ns->CFG_cache, ns->base + CFG);
writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG);
writel(ns->CFG_cache, ns->base + CFG);
writel(readl(dev->base + 0x20c) | 0xfe00,
writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
writel(0, ns->base + PQCR);
writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR);
writel(VTCR_PPCHK, ns->base + VTCR);
writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
writel(0, ns->base + WCSR);
#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tg3.regs + (reg))
writel(0x00000001, ioaddr + PCIBusCfg);
writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr);
writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr);
writel(0xE010, ioaddr + PCIBusCfg);
writel(0, ioaddr + RxStartDemand);
writel(intr_stat & 0x001ffff, ioaddr + IntrStatus);
writel(0, ioaddr + RxStartDemand);
writel(0, ioaddr + TxStartDemand);
writel(w840private.csr6 &= ~0x20FA, ioaddr + NetworkConfig);
writel(0x00000001, ioaddr + PCIBusCfg);
writel(EE_ChipSelect, ee_addr);
writel(dataval, ee_addr);
writel(dataval | EE_ShiftClk, ee_addr);
writel(EE_ChipSelect, ee_addr);
writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
writel(EE_ChipSelect, ee_addr);
writel(0, ee_addr);
writel(MDIO_WRITE1, mdio_addr);
writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
writel(dataval, mdio_addr);
writel(dataval | MDIO_ShiftClk, mdio_addr);
writel(MDIO_EnbIn, mdio_addr);
writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
writel(dataval, mdio_addr);
writel(dataval | MDIO_ShiftClk, mdio_addr);
writel(MDIO_EnbIn, mdio_addr);
writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
writel(mc_filter[0], ioaddr + MulticastFilter0);
writel(mc_filter[1], ioaddr + MulticastFilter1);
writel(w840private.csr6, ioaddr + NetworkConfig);