usr/src/cmd/cxgbetool/cxgbetool.c

484

write_reg(iff_name, addr, val);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

1399

write_reg(dev, SA, 0);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

1401

write_reg(dev, AIE, 0); /* Disable audio interrupts */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

239

write_reg(dev, SPC, 0x00000f00);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

241

write_reg(dev, SPC, 0x0000000f);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

253

write_reg(dev, I2C_1, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

258

write_reg(dev, I2C_A, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

287

write_reg(dev, SPI, orig | data);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

359

write_reg(dev, SA, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

368

write_reg(dev, SA, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

391

write_reg(dev, SA, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

397

write_reg(dev, SA, tmp);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

691

write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

692

write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

695

write_reg(dev, SA, 0);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

741

write_reg(dev, SCS0, 0x02108004); /* Audio */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

742

write_reg(dev, SCS1, 0x02108004); /* Audio */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

743

write_reg(dev, SCS2, 0x02108004); /* Audio */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

744

write_reg(dev, SCS3, 0x02108004); /* Audio */

usr/src/uts/common/io/audio/drv/audiols/audiols.c

798

write_reg(dev, HMIXMAP_I2S, r);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

810

write_reg(dev, P17RECVOLL, 0x30303030);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

811

write_reg(dev, P17RECVOLH, 0x30303030);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

818

write_reg(dev, P17RECVOLL, r);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

819

write_reg(dev, P17RECVOLH, r);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

826

write_reg(dev, SMIXMAP_I2S, 0x10101076);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

832

write_reg(dev, SMIXMAP_I2S, 0x10101076);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

834

write_reg(dev, SMIXMAP_I2S, 0x10101010);

usr/src/uts/common/io/audio/drv/audiols/audiols.c

883

write_reg(dev, P17RECSEL, r);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

239

write_reg(dev, CRFA, 0, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

240

write_reg(dev, CRCAV, 0, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

246

write_reg(dev, PTBA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

247

write_reg(dev, PTBS, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

248

write_reg(dev, PTCA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

249

write_reg(dev, PFEA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

250

write_reg(dev, CPFA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

251

write_reg(dev, CPCAV, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

499

write_reg(dev, PTBA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

500

write_reg(dev, PTBS, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

501

write_reg(dev, PTCA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

502

write_reg(dev, PFEA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

503

write_reg(dev, CPFA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

504

write_reg(dev, CPCAV, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

505

write_reg(dev, CRFA, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

506

write_reg(dev, CRCAV, i, 0);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

508

write_reg(dev, SCS0, 0, 0x02108504);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

509

write_reg(dev, SCS1, 0, 0x02108504);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

510

write_reg(dev, SCS2, 0, 0x02108504);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

513

write_reg(dev, SPC, 0, 0x00000700);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

514

write_reg(dev, EA_aux, 0, 0x0001003f);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

518

write_reg(dev, RFBA, 0, port->buf_paddr);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

519

write_reg(dev, RFBS, 0, (port->buf_size) << 16);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

525

write_reg(dev, PFBA, 0, paddr);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

526

write_reg(dev, PFBS, 0, chunksz << 16);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

528

write_reg(dev, PFBA, 1, paddr);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

529

write_reg(dev, PFBS, 1, chunksz << 16);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

531

write_reg(dev, PFBA, 2, paddr);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

532

write_reg(dev, PFBS, 2, chunksz << 16);

usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c

764

write_reg(dev, SA, 0, 0);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1058

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1098

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1131

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1150

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1161

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1175

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

122

phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1320

return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

1368

return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

681

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

696

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_80003es2lan.c

744

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_82540.c

435

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_82540.c

513

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,

usr/src/uts/common/io/e1000api/e1000_82540.c

544

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);

usr/src/uts/common/io/e1000api/e1000_82540.c

553

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_82540.c

559

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);

usr/src/uts/common/io/e1000api/e1000_82540.c

568

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_82540.c

572

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,

usr/src/uts/common/io/e1000api/e1000_82540.c

605

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,

usr/src/uts/common/io/e1000api/e1000_82540.c

611

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,

usr/src/uts/common/io/e1000api/e1000_82540.c

84

phy->ops.write_reg = e1000_write_phy_reg_m88;

usr/src/uts/common/io/e1000api/e1000_82541.c

1000

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

1010

ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);

usr/src/uts/common/io/e1000api/e1000_82541.c

1021

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

usr/src/uts/common/io/e1000api/e1000_82541.c

1048

ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,

usr/src/uts/common/io/e1000api/e1000_82541.c

106

phy->ops.write_reg = e1000_write_phy_reg_igp;

usr/src/uts/common/io/e1000api/e1000_82541.c

1074

ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,

usr/src/uts/common/io/e1000api/e1000_82541.c

1114

hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);

usr/src/uts/common/io/e1000api/e1000_82541.c

1118

hw->phy.ops.write_reg(hw, 0x0000, 0x0140);

usr/src/uts/common/io/e1000api/e1000_82541.c

1125

hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);

usr/src/uts/common/io/e1000api/e1000_82541.c

1127

hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);

usr/src/uts/common/io/e1000api/e1000_82541.c

1129

hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);

usr/src/uts/common/io/e1000api/e1000_82541.c

1131

hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);

usr/src/uts/common/io/e1000api/e1000_82541.c

1133

hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);

usr/src/uts/common/io/e1000api/e1000_82541.c

1135

hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);

usr/src/uts/common/io/e1000api/e1000_82541.c

1137

hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);

usr/src/uts/common/io/e1000api/e1000_82541.c

1139

hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);

usr/src/uts/common/io/e1000api/e1000_82541.c

1141

hw->phy.ops.write_reg(hw, 0x2010, 0x0008);

usr/src/uts/common/io/e1000api/e1000_82541.c

1145

hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);

usr/src/uts/common/io/e1000api/e1000_82541.c

1151

hw->phy.ops.write_reg(hw, 0x0000, 0x3300);

usr/src/uts/common/io/e1000api/e1000_82541.c

1156

hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);

usr/src/uts/common/io/e1000api/e1000_82541.c

1183

hw->phy.ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

1186

hw->phy.ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

713

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

744

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

768

ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);

usr/src/uts/common/io/e1000api/e1000_82541.c

774

ret_val = phy->ops.write_reg(hw, 0x0000,

usr/src/uts/common/io/e1000api/e1000_82541.c

788

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82541.c

795

ret_val = phy->ops.write_reg(hw, 0x0000,

usr/src/uts/common/io/e1000api/e1000_82541.c

803

ret_val = phy->ops.write_reg(hw, 0x2F5B,

usr/src/uts/common/io/e1000api/e1000_82541.c

825

ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);

usr/src/uts/common/io/e1000api/e1000_82541.c

831

ret_val = phy->ops.write_reg(hw, 0x0000,

usr/src/uts/common/io/e1000api/e1000_82541.c

836

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,

usr/src/uts/common/io/e1000api/e1000_82541.c

841

ret_val = phy->ops.write_reg(hw, 0x0000,

usr/src/uts/common/io/e1000api/e1000_82541.c

849

ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);

usr/src/uts/common/io/e1000api/e1000_82541.c

969

ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);

usr/src/uts/common/io/e1000api/e1000_82541.c

987

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82543.c

116

phy->ops.write_reg = (hw->mac.type == e1000_82543)

usr/src/uts/common/io/e1000api/e1000_82543.c

774

if (!(hw->phy.ops.write_reg))

usr/src/uts/common/io/e1000api/e1000_82543.c

781

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);

usr/src/uts/common/io/e1000api/e1000_82543.c

784

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);

usr/src/uts/common/io/e1000api/e1000_82543.c

788

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);

usr/src/uts/common/io/e1000api/e1000_82543.c

820

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);

usr/src/uts/common/io/e1000api/e1000_82543.c

824

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);

usr/src/uts/common/io/e1000api/e1000_82543.c

828

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);

usr/src/uts/common/io/e1000api/e1000_82543.c

832

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);

usr/src/uts/common/io/e1000api/e1000_82543.c

836

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);

usr/src/uts/common/io/e1000api/e1000_82571.c

1003

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_82571.c

1014

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

usr/src/uts/common/io/e1000api/e1000_82571.c

1020

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_82571.c

1035

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82571.c

1048

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82571.c

127

phy->ops.write_reg = e1000_write_phy_reg_igp;

usr/src/uts/common/io/e1000api/e1000_82571.c

140

phy->ops.write_reg = e1000_write_phy_reg_m88;

usr/src/uts/common/io/e1000api/e1000_82571.c

156

phy->ops.write_reg = e1000_write_phy_reg_bm2;

usr/src/uts/common/io/e1000api/e1000_82575.c

1244

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

1256

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);

usr/src/uts/common/io/e1000api/e1000_82575.c

1275

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

1282

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

207

phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;

usr/src/uts/common/io/e1000api/e1000_82575.c

214

phy->ops.write_reg = e1000_write_phy_reg_82580;

usr/src/uts/common/io/e1000api/e1000_82575.c

219

phy->ops.write_reg = e1000_write_phy_reg_gs40g;

usr/src/uts/common/io/e1000api/e1000_82575.c

223

phy->ops.write_reg = e1000_write_phy_reg_igp;

usr/src/uts/common/io/e1000api/e1000_82575.c

257

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82575.c

2798

ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);

usr/src/uts/common/io/e1000api/e1000_82575.c

2805

ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);

usr/src/uts/common/io/e1000api/e1000_82575.c

2841

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);

usr/src/uts/common/io/e1000api/e1000_82575.c

2845

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);

usr/src/uts/common/io/e1000api/e1000_82575.c

2849

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);

usr/src/uts/common/io/e1000api/e1000_82575.c

2853

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);

usr/src/uts/common/io/e1000api/e1000_82575.c

2857

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);

usr/src/uts/common/io/e1000api/e1000_82575.c

2861

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);

usr/src/uts/common/io/e1000api/e1000_82575.c

2865

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);

usr/src/uts/common/io/e1000api/e1000_82575.c

2869

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);

usr/src/uts/common/io/e1000api/e1000_82575.c

2873

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);

usr/src/uts/common/io/e1000api/e1000_82575.c

2878

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);

usr/src/uts/common/io/e1000api/e1000_82575.c

2882

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);

usr/src/uts/common/io/e1000api/e1000_82575.c

2887

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);

usr/src/uts/common/io/e1000api/e1000_82575.c

2892

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);

usr/src/uts/common/io/e1000api/e1000_82575.c

2897

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

2930

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);

usr/src/uts/common/io/e1000api/e1000_82575.c

2934

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);

usr/src/uts/common/io/e1000api/e1000_82575.c

2938

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);

usr/src/uts/common/io/e1000api/e1000_82575.c

2942

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);

usr/src/uts/common/io/e1000api/e1000_82575.c

2946

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);

usr/src/uts/common/io/e1000api/e1000_82575.c

2950

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);

usr/src/uts/common/io/e1000api/e1000_82575.c

2954

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);

usr/src/uts/common/io/e1000api/e1000_82575.c

2958

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);

usr/src/uts/common/io/e1000api/e1000_82575.c

2962

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);

usr/src/uts/common/io/e1000api/e1000_82575.c

2967

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);

usr/src/uts/common/io/e1000api/e1000_82575.c

2971

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);

usr/src/uts/common/io/e1000api/e1000_82575.c

2976

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);

usr/src/uts/common/io/e1000api/e1000_82575.c

2981

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);

usr/src/uts/common/io/e1000api/e1000_82575.c

2986

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);

usr/src/uts/common/io/e1000api/e1000_82575.c

2991

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);

usr/src/uts/common/io/e1000api/e1000_82575.c

2996

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

3090

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);

usr/src/uts/common/io/e1000api/e1000_82575.c

3100

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,

usr/src/uts/common/io/e1000api/e1000_82575.c

3106

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

usr/src/uts/common/io/e1000api/e1000_82575.c

777

if (!(hw->phy.ops.write_reg))

usr/src/uts/common/io/e1000api/e1000_82575.c

784

ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);

usr/src/uts/common/io/e1000api/e1000_82575.c

828

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_82575.c

837

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

usr/src/uts/common/io/e1000api/e1000_82575.c

843

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_82575.c

859

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_82575.c

872

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_api.c

1074

if (hw->phy.ops.write_reg)

usr/src/uts/common/io/e1000api/e1000_api.c

1075

return hw->phy.ops.write_reg(hw, offset, data);

usr/src/uts/common/io/e1000api/e1000_hw.h

831

s32 (*write_reg)(struct e1000_hw *, u32, u16);

usr/src/uts/common/io/e1000api/e1000_i210.c

763

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);

usr/src/uts/common/io/e1000api/e1000_i210.c

767

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);

usr/src/uts/common/io/e1000api/e1000_i210.c

771

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |

usr/src/uts/common/io/e1000api/e1000_i210.c

779

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);

usr/src/uts/common/io/e1000api/e1000_i210.c

784

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

1101

ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

1790

hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2647

ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2677

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2682

ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2694

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2816

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2884

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2889

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2895

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2898

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2902

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2942

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2947

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2953

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2956

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2960

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2967

return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3038

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3151

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3238

return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3288

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3313

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3326

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3381

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3394

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

3423

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

479

phy->ops.write_reg = e1000_write_phy_reg_hv;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5155

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5328

ret_val = hw->phy.ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5417

ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5618

hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

577

phy->ops.write_reg = e1000_write_phy_reg_igp;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

586

phy->ops.write_reg = e1000_write_phy_reg_bm;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5893

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5911

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5929

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5946

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5960

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

5993

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

6025

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

628

phy->ops.write_reg = e1000_write_phy_reg_bm;

usr/src/uts/common/io/e1000api/e1000_phy.c

1039

return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1073

ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1098

ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1170

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

1185

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1214

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

1222

ret_val = phy->ops.write_reg(hw, 29, 0x0003);

usr/src/uts/common/io/e1000api/e1000_phy.c

1227

ret_val = phy->ops.write_reg(hw, 30, 0x0000);

usr/src/uts/common/io/e1000api/e1000_phy.c

1248

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

1321

phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1336

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1420

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1439

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_phy.c

1451

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1602

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

usr/src/uts/common/io/e1000api/e1000_phy.c

1609

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

1659

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

usr/src/uts/common/io/e1000api/e1000_phy.c

1756

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1770

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1827

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

1841

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1882

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_phy.c

1921

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1933

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1961

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);

usr/src/uts/common/io/e1000api/e1000_phy.c

1973

ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);

usr/src/uts/common/io/e1000api/e1000_phy.c

2094

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_phy.c

2111

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_phy.c

2124

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/e1000api/e1000_phy.c

2134

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

usr/src/uts/common/io/e1000api/e1000_phy.c

2146

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

usr/src/uts/common/io/e1000api/e1000_phy.c

2474

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);

usr/src/uts/common/io/e1000api/e1000_phy.c

2497

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,

usr/src/uts/common/io/e1000api/e1000_phy.c

2510

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);

usr/src/uts/common/io/e1000api/e1000_phy.c

2532

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,

usr/src/uts/common/io/e1000api/e1000_phy.c

265

if (!hw->phy.ops.write_reg)

usr/src/uts/common/io/e1000api/e1000_phy.c

268

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

usr/src/uts/common/io/e1000api/e1000_phy.c

272

return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);

usr/src/uts/common/io/e1000api/e1000_phy.c

2833

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

usr/src/uts/common/io/e1000api/e1000_phy.c

2913

hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);

usr/src/uts/common/io/e1000api/e1000_phy.c

2915

hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);

usr/src/uts/common/io/e1000api/e1000_phy.c

2917

hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);

usr/src/uts/common/io/e1000api/e1000_phy.c

2919

hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);

usr/src/uts/common/io/e1000api/e1000_phy.c

2921

hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);

usr/src/uts/common/io/e1000api/e1000_phy.c

2923

hw->phy.ops.write_reg(hw, 0x2011, 0x0000);

usr/src/uts/common/io/e1000api/e1000_phy.c

2925

hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);

usr/src/uts/common/io/e1000api/e1000_phy.c

2927

hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);

usr/src/uts/common/io/e1000api/e1000_phy.c

2929

hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);

usr/src/uts/common/io/e1000api/e1000_phy.c

2931

hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);

usr/src/uts/common/io/e1000api/e1000_phy.c

2933

hw->phy.ops.write_reg(hw, 0x0000, 0x0140);

usr/src/uts/common/io/e1000api/e1000_phy.c

2935

hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);

usr/src/uts/common/io/e1000api/e1000_phy.c

2937

hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);

usr/src/uts/common/io/e1000api/e1000_phy.c

2939

hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);

usr/src/uts/common/io/e1000api/e1000_phy.c

2941

hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);

usr/src/uts/common/io/e1000api/e1000_phy.c

2943

hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);

usr/src/uts/common/io/e1000api/e1000_phy.c

2945

hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);

usr/src/uts/common/io/e1000api/e1000_phy.c

2947

hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);

usr/src/uts/common/io/e1000api/e1000_phy.c

2949

hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);

usr/src/uts/common/io/e1000api/e1000_phy.c

2951

hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);

usr/src/uts/common/io/e1000api/e1000_phy.c

2953

hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);

usr/src/uts/common/io/e1000api/e1000_phy.c

2955

hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);

usr/src/uts/common/io/e1000api/e1000_phy.c

2957

hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);

usr/src/uts/common/io/e1000api/e1000_phy.c

2959

hw->phy.ops.write_reg(hw, 0x1895, 0x0003);

usr/src/uts/common/io/e1000api/e1000_phy.c

2961

hw->phy.ops.write_reg(hw, 0x1796, 0x0008);

usr/src/uts/common/io/e1000api/e1000_phy.c

2963

hw->phy.ops.write_reg(hw, 0x1798, 0xD008);

usr/src/uts/common/io/e1000api/e1000_phy.c

2967

hw->phy.ops.write_reg(hw, 0x1898, 0xD918);

usr/src/uts/common/io/e1000api/e1000_phy.c

2969

hw->phy.ops.write_reg(hw, 0x187A, 0x0800);

usr/src/uts/common/io/e1000api/e1000_phy.c

2973

hw->phy.ops.write_reg(hw, 0x0019, 0x008D);

usr/src/uts/common/io/e1000api/e1000_phy.c

2975

hw->phy.ops.write_reg(hw, 0x001B, 0x2080);

usr/src/uts/common/io/e1000api/e1000_phy.c

2977

hw->phy.ops.write_reg(hw, 0x0014, 0x0045);

usr/src/uts/common/io/e1000api/e1000_phy.c

2979

hw->phy.ops.write_reg(hw, 0x0000, 0x1340);

usr/src/uts/common/io/e1000api/e1000_phy.c

3499

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

usr/src/uts/common/io/e1000api/e1000_phy.c

3517

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

usr/src/uts/common/io/e1000api/e1000_phy.c

3859

ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

3865

return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,

usr/src/uts/common/io/e1000api/e1000_phy.c

3916

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

usr/src/uts/common/io/e1000api/e1000_phy.c

93

phy->ops.write_reg = e1000_null_write_reg;

usr/src/uts/common/io/e1000g/e1000g_workarounds.c

269

hw->phy.ops.write_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value);

usr/src/uts/common/io/igc/core/igc_api.c

470

if (hw->phy.ops.write_reg)

usr/src/uts/common/io/igc/core/igc_api.c

471

return hw->phy.ops.write_reg(hw, offset, data);

usr/src/uts/common/io/igc/core/igc_hw.h

394

s32 (*write_reg)(struct igc_hw *, u32, u16);

usr/src/uts/common/io/igc/core/igc_i225.c

157

phy->ops.write_reg = igc_write_phy_reg_gpy;

usr/src/uts/common/io/igc/core/igc_phy.c

1017

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);

usr/src/uts/common/io/igc/core/igc_phy.c

1021

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);

usr/src/uts/common/io/igc/core/igc_phy.c

1025

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |

usr/src/uts/common/io/igc/core/igc_phy.c

1033

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);

usr/src/uts/common/io/igc/core/igc_phy.c

1038

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);

usr/src/uts/common/io/igc/core/igc_phy.c

36

phy->ops.write_reg = igc_null_write_reg;

usr/src/uts/common/io/igc/core/igc_phy.c

440

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

usr/src/uts/common/io/igc/core/igc_phy.c

447

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

usr/src/uts/common/io/igc/core/igc_phy.c

451

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/igc/core/igc_phy.c

504

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

usr/src/uts/common/io/igc/core/igc_phy.c

670

ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,

usr/src/uts/common/io/igc/core/igc_phy.c

687

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/igc/core/igc_phy.c

700

ret_val = phy->ops.write_reg(hw,

usr/src/uts/common/io/igc/core/igc_phy.c

710

ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,

usr/src/uts/common/io/igc/core/igc_phy.c

722

ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,

usr/src/uts/common/io/igc/core/igc_phy.c

912

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

usr/src/uts/common/io/igc/core/igc_phy.c

931

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

600

return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_common.c

381

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

usr/src/uts/common/io/ixgbe/core/ixgbe_e610.c

4604

phy->ops.write_reg = NULL;

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

1062

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

1077

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

1092

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

1162

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

1217

hw->phy.ops.write_reg(hw, phy_offset,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

257

phy->ops.write_reg = ixgbe_write_phy_reg_generic;

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

2714

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

521

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

585

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

825

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

854

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

869

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

usr/src/uts/common/io/ixgbe/core/ixgbe_type.h

4155

s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2016

status = hw->phy.ops.write_reg(hw,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2035

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2053

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2070

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2236

hw->phy.ops.write_reg = NULL;

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2247

hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2280

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2285

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2296

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2527

status = hw->phy.ops.write_reg(hw,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

2744

ret_val = hw->phy.ops.write_reg(hw, reg_slice,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

502

hw->phy.ops.write_reg = NULL;