usr/src/uts/intel/io/vmm/intel/vmx.c

3900

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

3910

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

3920

error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

3929

error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

3937

error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

3945

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

470

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

487

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

498

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

506

error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

517

error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

528

error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

541

cap_monitor_trap = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

546

cap_pause_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

551

cap_wbinvd_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

556

cap_invpcid = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

566

if (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, MSR_VMX_TRUE_PROCBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx.c

575

if (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

586

error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS,

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

54

int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,