usr/src/cmd/bhyve/amd64/vmexit.c

380

EPRINTLN("\tstatus\t\t%d", vme->u.vmx.status);

usr/src/cmd/bhyve/amd64/vmexit.c

381

EPRINTLN("\texit_reason\t%u (%s)", vme->u.vmx.exit_reason,

usr/src/cmd/bhyve/amd64/vmexit.c

382

vmexit_vmx_desc(vme->u.vmx.exit_reason));

usr/src/cmd/bhyve/amd64/vmexit.c

384

vme->u.vmx.exit_qualification);

usr/src/cmd/bhyve/amd64/vmexit.c

385

EPRINTLN("\tinst_type\t\t%d", vme->u.vmx.inst_type);

usr/src/cmd/bhyve/amd64/vmexit.c

386

EPRINTLN("\tinst_error\t\t%d", vme->u.vmx.inst_error);

usr/src/cmd/bhyve/amd64/vmexit.c

388

if (vme->u.vmx.exit_reason == EXIT_REASON_EPT_MISCONFIG) {

usr/src/cmd/bhyvectl/bhyvectl.c

195

printf("\tstatus\t\t%d\n", vmexit->u.vmx.status);

usr/src/cmd/bhyvectl/bhyvectl.c

197

vmexit->u.vmx.exit_reason, vmexit->u.vmx.exit_reason);

usr/src/cmd/bhyvectl/bhyvectl.c

199

vmexit->u.vmx.exit_qualification);

usr/src/cmd/bhyvectl/bhyvectl.c

200

printf("\tinst_type\t\t%d\n", vmexit->u.vmx.inst_type);

usr/src/cmd/bhyvectl/bhyvectl.c

201

printf("\tinst_error\t\t%d\n", vmexit->u.vmx.inst_error);

usr/src/test/bhyve-tests/tests/common/in_guest.c

238

vexit->u.vmx.status,

usr/src/test/bhyve-tests/tests/common/in_guest.c

239

vexit->u.vmx.exit_reason,

usr/src/test/bhyve-tests/tests/common/in_guest.c

240

vexit->u.vmx.exit_qualification,

usr/src/test/bhyve-tests/tests/common/in_guest.c

241

vexit->u.vmx.inst_type,

usr/src/test/bhyve-tests/tests/common/in_guest.c

242

vexit->u.vmx.inst_error);

usr/src/test/bhyve-tests/tests/kdev/vlapic_mmio_access.c

104

(vexit.u.vmx.exit_reason == 44 ||

usr/src/test/bhyve-tests/tests/kdev/vlapic_mmio_access.c

105

vexit.u.vmx.exit_reason == 56)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1013

vmx_set_pcpu_defaults(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1029

vmx_apply_tsc_adjust(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1031

vmxstate = &vmx->state[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

1037

vmm_stat_incr(vmx->vm, vcpu, VCPU_MIGRATIONS, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

1044

vmx_invvpid(vmx, vcpu, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

1048

vmx_int_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1050

return ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

1054

vmx_set_int_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1056

if (!vmx_int_window_exiting(vmx, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1058

vmx->cap[vcpu].proc_ctls |= PROCBASED_INT_WINDOW_EXITING;

usr/src/uts/intel/io/vmm/intel/vmx.c

1059

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1064

vmx_clear_int_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1067

vmx->cap[vcpu].proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING;

usr/src/uts/intel/io/vmm/intel/vmx.c

1068

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1072

vmx_nmi_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1074

return ((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

1078

vmx_set_nmi_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1080

if (!vmx_nmi_window_exiting(vmx, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1081

vmx->cap[vcpu].proc_ctls |= PROCBASED_NMI_WINDOW_EXITING;

usr/src/uts/intel/io/vmm/intel/vmx.c

1082

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1087

vmx_clear_nmi_window_exiting(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1089

vmx->cap[vcpu].proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING;

usr/src/uts/intel/io/vmm/intel/vmx.c

1090

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1101

vmx_apply_tsc_adjust(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1103

const uint64_t offset = vcpu_tsc_offset(vmx->vm, vcpu, true);

usr/src/uts/intel/io/vmm/intel/vmx.c

1105

ASSERT(vmx->cap[vcpu].proc_ctls & PROCBASED_TSC_OFFSET);

usr/src/uts/intel/io/vmm/intel/vmx.c

1107

if (vmx->tsc_offset_active[vcpu] != offset) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1109

vmx->tsc_offset_active[vcpu] = offset;

usr/src/uts/intel/io/vmm/intel/vmx.c

1159

vmx_stash_intinfo(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1169

VERIFY0(vm_exit_intinfo(vmx->vm, vcpu,

usr/src/uts/intel/io/vmm/intel/vmx.c

1215

vmx_inject_nmi(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

1228

vm_nmi_clear(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1241

vmx_inject_events(struct vmx *vmx, int vcpu, uint64_t rip)

usr/src/uts/intel/io/vmm/intel/vmx.c

1253

if (vmx->state[vcpu].nextrip != rip && (gi & HWINTR_BLOCKING) != 0) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1267

if (vm_entry_intinfo(vmx->vm, vcpu, &entryinfo)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1272

if (vm_nmi_pending(vmx->vm, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1286

vmx_inject_nmi(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1292

vmx_set_nmi_window_exiting(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1296

if (vm_extint_pending(vmx->vm, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1306

vatpic_pending_intr(vmx->vm, &vector);

usr/src/uts/intel/io/vmm/intel/vmx.c

1321

vm_extint_clear(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1322

vatpic_intr_accepted(vmx->vm, vector);

usr/src/uts/intel/io/vmm/intel/vmx.c

1337

vmx_inject_vlapic(struct vmx *vmx, int vcpu, struct vlapic *vlapic)

usr/src/uts/intel/io/vmm/intel/vmx.c

1354

if (vmx_cap_en(vmx, VMX_CAP_APICV)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1407

vmx_inject_recheck(struct vmx *vmx, int vcpu, enum event_inject_state state)

usr/src/uts/intel/io/vmm/intel/vmx.c

1410

if (vm_nmi_pending(vmx->vm, vcpu) &&

usr/src/uts/intel/io/vmm/intel/vmx.c

1411

!vmx_nmi_window_exiting(vmx, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1415

if (vm_extint_pending(vmx->vm, vcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1433

vmx_set_int_window_exiting(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1449

vmx_restore_nmi_blocking(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

1459

vmx_clear_nmi_blocking(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

1469

vmx_assert_nmi_blocking(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

1479

vmx_emulate_xsetbv(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)

usr/src/uts/intel/io/vmm/intel/vmx.c

1485

vmxctx = &vmx->ctx[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

1496

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1503

vm_inject_ud(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1509

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1514

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1521

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1532

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1542

vm_inject_gp(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1556

vmx_get_guest_reg(struct vmx *vmx, int vcpu, int ident)

usr/src/uts/intel/io/vmm/intel/vmx.c

1560

vmxctx = &vmx->ctx[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

1601

vmx_set_guest_reg(struct vmx *vmx, int vcpu, int ident, uint64_t regval)

usr/src/uts/intel/io/vmm/intel/vmx.c

1605

vmxctx = &vmx->ctx[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

1662

vmx_sync_efer_state(struct vmx *vmx, int vcpu, uint64_t efer)

usr/src/uts/intel/io/vmm/intel/vmx.c

1681

vmx_emulate_cr0_access(struct vmx *vmx, int vcpu, uint64_t exitqual)

usr/src/uts/intel/io/vmm/intel/vmx.c

1689

regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);

usr/src/uts/intel/io/vmm/intel/vmx.c

1700

vmx_invvpid(vmx, vcpu, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

1713

vmx_sync_efer_state(vmx, vcpu, efer);

usr/src/uts/intel/io/vmm/intel/vmx.c

172

SYSCTL_NODE(_hw_vmm, OID_AUTO, vmx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,

usr/src/uts/intel/io/vmm/intel/vmx.c

1721

vmx_emulate_cr4_access(struct vmx *vmx, int vcpu, uint64_t exitqual)

usr/src/uts/intel/io/vmm/intel/vmx.c

1729

regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);

usr/src/uts/intel/io/vmm/intel/vmx.c

1741

vmx_emulate_cr8_access(struct vmx *vmx, int vcpu, uint64_t exitqual)

usr/src/uts/intel/io/vmm/intel/vmx.c

1752

vlapic = vm_lapic(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

1756

vmx_set_guest_reg(vmx, vcpu, regnum, cr8);

usr/src/uts/intel/io/vmm/intel/vmx.c

1758

cr8 = vmx_get_guest_reg(vmx, vcpu, regnum);

usr/src/uts/intel/io/vmm/intel/vmx.c

1949

apic_access_virtualization(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

1953

proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;

usr/src/uts/intel/io/vmm/intel/vmx.c

1958

x2apic_virtualization(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

1962

proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;

usr/src/uts/intel/io/vmm/intel/vmx.c

1967

vmx_handle_apic_write(struct vmx *vmx, int vcpuid, struct vlapic *vlapic,

usr/src/uts/intel/io/vmm/intel/vmx.c

1972

if (!apic_access_virtualization(vmx, vcpuid)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

1980

if (x2apic_virtualization(vmx, vcpuid) &&

usr/src/uts/intel/io/vmm/intel/vmx.c

2029

apic_access_fault(struct vmx *vmx, int vcpuid, uint64_t gpa)

usr/src/uts/intel/io/vmm/intel/vmx.c

2032

if (apic_access_virtualization(vmx, vcpuid) &&

usr/src/uts/intel/io/vmm/intel/vmx.c

2040

vmx_handle_apic_access(struct vmx *vmx, int vcpuid, struct vm_exit *vmexit)

usr/src/uts/intel/io/vmm/intel/vmx.c

2046

if (!apic_access_virtualization(vmx, vcpuid))

usr/src/uts/intel/io/vmm/intel/vmx.c

2049

qual = vmexit->u.vmx.exit_qualification;

usr/src/uts/intel/io/vmm/intel/vmx.c

2091

vie = vm_vie_ctx(vmx->vm, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

2128

vmx_handle_msr(struct vmx *vmx, int vcpuid, struct vm_exit *vmexit,

usr/src/uts/intel/io/vmm/intel/vmx.c

2131

struct vmxctx *vmxctx = &vmx->ctx[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx.c

2137

vmm_stat_incr(vmx->vm, vcpuid, VMEXIT_WRMSR, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2141

struct vlapic *vlapic = vm_lapic(vmx->vm, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

2145

res = vmx_wrmsr(vmx, vcpuid, ecx, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

2148

vmm_stat_incr(vmx->vm, vcpuid, VMEXIT_RDMSR, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2151

struct vlapic *vlapic = vm_lapic(vmx->vm, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

2155

res = vmx_rdmsr(vmx, vcpuid, ecx, &val);

usr/src/uts/intel/io/vmm/intel/vmx.c

2168

vm_inject_gp(vmx->vm, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

2182

vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)

usr/src/uts/intel/io/vmm/intel/vmx.c

2197

vmxctx = &vmx->ctx[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

2199

qual = vmexit->u.vmx.exit_qualification;

usr/src/uts/intel/io/vmm/intel/vmx.c

2200

reason = vmexit->u.vmx.exit_reason;

usr/src/uts/intel/io/vmm/intel/vmx.c

2203

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_COUNT, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2204

SDT_PROBE3(vmm, vmx, exit, entry, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2233

VERIFY0(vm_exit_intinfo(vmx->vm, vcpu,

usr/src/uts/intel/io/vmm/intel/vmx.c

2250

vmx_clear_nmi_blocking(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2252

vmx_assert_nmi_blocking(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2268

(void) vm_suspend(vmx->vm, VM_SUSPEND_TRIPLEFAULT, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

229

SDT_PROBE_DEFINE3(vmm, vmx, exit, entry,

usr/src/uts/intel/io/vmm/intel/vmx.c

2310

SDT_PROBE4(vmm, vmx, exit, taskswitch, vmx, vcpu, vmexit, ts);

usr/src/uts/intel/io/vmm/intel/vmx.c

2313

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CR_ACCESS, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2314

SDT_PROBE4(vmm, vmx, exit, craccess, vmx, vcpu, vmexit, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

2317

handled = vmx_emulate_cr0_access(vmx, vcpu, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

232

SDT_PROBE_DEFINE4(vmm, vmx, exit, taskswitch,

usr/src/uts/intel/io/vmm/intel/vmx.c

2320

handled = vmx_emulate_cr4_access(vmx, vcpu, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

2323

handled = vmx_emulate_cr8_access(vmx, vcpu, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

2329

handled = vmx_handle_msr(vmx, vcpu, vmexit,

usr/src/uts/intel/io/vmm/intel/vmx.c

2333

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_HLT, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2334

SDT_PROBE3(vmm, vmx, exit, halt, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2339

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_MTRAP, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2340

SDT_PROBE3(vmm, vmx, exit, mtrap, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2345

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_PAUSE, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2346

SDT_PROBE3(vmm, vmx, exit, pause, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

235

SDT_PROBE_DEFINE4(vmm, vmx, exit, craccess,

usr/src/uts/intel/io/vmm/intel/vmx.c

2350

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INTR_WINDOW, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2351

SDT_PROBE3(vmm, vmx, exit, intrwindow, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2352

ASSERT(vmx_int_window_exiting(vmx, vcpu));

usr/src/uts/intel/io/vmm/intel/vmx.c

2353

vmx_clear_int_window_exiting(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2366

SDT_PROBE4(vmm, vmx, exit, interrupt,

usr/src/uts/intel/io/vmm/intel/vmx.c

2367

vmx, vcpu, vmexit, intr_info);

usr/src/uts/intel/io/vmm/intel/vmx.c

238

SDT_PROBE_DEFINE4(vmm, vmx, exit, rdmsr,

usr/src/uts/intel/io/vmm/intel/vmx.c

2384

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXTINT, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2387

SDT_PROBE3(vmm, vmx, exit, nmiwindow, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2389

if (vm_nmi_pending(vmx->vm, vcpu))

usr/src/uts/intel/io/vmm/intel/vmx.c

2390

vmx_inject_nmi(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2391

ASSERT(vmx_nmi_window_exiting(vmx, vcpu));

usr/src/uts/intel/io/vmm/intel/vmx.c

2392

vmx_clear_nmi_window_exiting(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2393

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NMI_WINDOW, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2396

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INOUT, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2397

vie = vm_vie_ctx(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2399

SDT_PROBE3(vmm, vmx, exit, inout, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2402

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CPUID, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2403

SDT_PROBE3(vmm, vmx, exit, cpuid, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2404

vcpu_emulate_cpuid(vmx->vm, vcpu,

usr/src/uts/intel/io/vmm/intel/vmx.c

241

SDT_PROBE_DEFINE5(vmm, vmx, exit, wrmsr,

usr/src/uts/intel/io/vmm/intel/vmx.c

2412

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXCEPTION, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2432

vmx_restore_nmi_blocking(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

244

SDT_PROBE_DEFINE3(vmm, vmx, exit, halt,

usr/src/uts/intel/io/vmm/intel/vmx.c

2455

(vmx->cap[vcpu].set & (1 << VM_CAP_BPT_EXIT))) {

usr/src/uts/intel/io/vmm/intel/vmx.c

247

SDT_PROBE_DEFINE3(vmm, vmx, exit, mtrap,

usr/src/uts/intel/io/vmm/intel/vmx.c

2481

SDT_PROBE5(vmm, vmx, exit, exception,

usr/src/uts/intel/io/vmm/intel/vmx.c

2482

vmx, vcpu, vmexit, intr_vec, errcode);

usr/src/uts/intel/io/vmm/intel/vmx.c

2483

error = vm_inject_exception(vmx->vm, vcpu, intr_vec,

usr/src/uts/intel/io/vmm/intel/vmx.c

2496

if (vm_mem_allocated(vmx->vm, vcpu, gpa) ||

usr/src/uts/intel/io/vmm/intel/vmx.c

2497

apic_access_fault(vmx, vcpu, gpa)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

250

SDT_PROBE_DEFINE3(vmm, vmx, exit, pause,

usr/src/uts/intel/io/vmm/intel/vmx.c

2502

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NESTED_FAULT, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2503

SDT_PROBE5(vmm, vmx, exit, nestedfault,

usr/src/uts/intel/io/vmm/intel/vmx.c

2504

vmx, vcpu, vmexit, gpa, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

2506

vie = vm_vie_ctx(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2509

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_MMIO_EMUL, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

2510

SDT_PROBE4(vmm, vmx, exit, mmiofault,

usr/src/uts/intel/io/vmm/intel/vmx.c

2511

vmx, vcpu, vmexit, gpa);

usr/src/uts/intel/io/vmm/intel/vmx.c

2523

vmx_restore_nmi_blocking(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2528

SDT_PROBE3(vmm, vmx, exit, eoi, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

253

SDT_PROBE_DEFINE3(vmm, vmx, exit, intrwindow,

usr/src/uts/intel/io/vmm/intel/vmx.c

2532

SDT_PROBE3(vmm, vmx, exit, apicaccess, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2533

handled = vmx_handle_apic_access(vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2541

vlapic = vm_lapic(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2542

SDT_PROBE4(vmm, vmx, exit, apicwrite,

usr/src/uts/intel/io/vmm/intel/vmx.c

2543

vmx, vcpu, vmexit, vlapic);

usr/src/uts/intel/io/vmm/intel/vmx.c

2544

handled = vmx_handle_apic_write(vmx, vcpu, vlapic, qual);

usr/src/uts/intel/io/vmm/intel/vmx.c

2547

SDT_PROBE3(vmm, vmx, exit, xsetbv, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2548

handled = vmx_emulate_xsetbv(vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2551

SDT_PROBE3(vmm, vmx, exit, monitor, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2555

SDT_PROBE3(vmm, vmx, exit, mwait, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2559

vlapic = vm_lapic(vmx->vm, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

256

SDT_PROBE_DEFINE4(vmm, vmx, exit, interrupt,

usr/src/uts/intel/io/vmm/intel/vmx.c

2574

SDT_PROBE3(vmm, vmx, exit, vminsn, vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

2583

SDT_PROBE4(vmm, vmx, exit, unknown,

usr/src/uts/intel/io/vmm/intel/vmx.c

2584

vmx, vcpu, vmexit, reason);

usr/src/uts/intel/io/vmm/intel/vmx.c

2585

vmm_stat_incr(vmx->vm, vcpu, VMEXIT_UNKNOWN, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

259

SDT_PROBE_DEFINE3(vmm, vmx, exit, nmiwindow,

usr/src/uts/intel/io/vmm/intel/vmx.c

2610

vmexit->u.vmx.status = VM_SUCCESS;

usr/src/uts/intel/io/vmm/intel/vmx.c

2611

vmexit->u.vmx.inst_type = 0;

usr/src/uts/intel/io/vmm/intel/vmx.c

2612

vmexit->u.vmx.inst_error = 0;

usr/src/uts/intel/io/vmm/intel/vmx.c

262

SDT_PROBE_DEFINE3(vmm, vmx, exit, inout,

usr/src/uts/intel/io/vmm/intel/vmx.c

2621

SDT_PROBE4(vmm, vmx, exit, return,

usr/src/uts/intel/io/vmm/intel/vmx.c

2622

vmx, vcpu, vmexit, handled);

usr/src/uts/intel/io/vmm/intel/vmx.c

2636

vmexit->u.vmx.status = vmxctx->inst_fail_status;

usr/src/uts/intel/io/vmm/intel/vmx.c

2637

vmexit->u.vmx.inst_error = vmcs_read(VMCS_INSTRUCTION_ERROR);

usr/src/uts/intel/io/vmm/intel/vmx.c

2638

vmexit->u.vmx.exit_reason = ~0;

usr/src/uts/intel/io/vmm/intel/vmx.c

2639

vmexit->u.vmx.exit_qualification = ~0;

usr/src/uts/intel/io/vmm/intel/vmx.c

2646

vmexit->u.vmx.inst_type = rc;

usr/src/uts/intel/io/vmm/intel/vmx.c

265

SDT_PROBE_DEFINE3(vmm, vmx, exit, cpuid,

usr/src/uts/intel/io/vmm/intel/vmx.c

2666

if (vmexit->u.vmx.exit_reason == EXIT_REASON_EXCEPTION) {

usr/src/uts/intel/io/vmm/intel/vmx.c

268

SDT_PROBE_DEFINE5(vmm, vmx, exit, exception,

usr/src/uts/intel/io/vmm/intel/vmx.c

271

SDT_PROBE_DEFINE5(vmm, vmx, exit, nestedfault,

usr/src/uts/intel/io/vmm/intel/vmx.c

274

SDT_PROBE_DEFINE4(vmm, vmx, exit, mmiofault,

usr/src/uts/intel/io/vmm/intel/vmx.c

2748

struct vmx *vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

2758

vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

2759

vm = vmx->vm;

usr/src/uts/intel/io/vmm/intel/vmx.c

2760

vmcs_pa = vmx->vmcs_pa[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

2761

vmxctx = &vmx->ctx[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

2766

tpr_shadow_active = vmx_cap_en(vmx, VMX_CAP_TPR_SHADOW) &&

usr/src/uts/intel/io/vmm/intel/vmx.c

2767

!vmx_cap_en(vmx, VMX_CAP_APICV) &&

usr/src/uts/intel/io/vmm/intel/vmx.c

2768

(vmx->cap[vcpu].proc_ctls & PROCBASED_USE_TPR_SHADOW) != 0;

usr/src/uts/intel/io/vmm/intel/vmx.c

277

SDT_PROBE_DEFINE3(vmm, vmx, exit, eoi,

usr/src/uts/intel/io/vmm/intel/vmx.c

2770

vmx_msr_guest_enter(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2774

VERIFY(vmx->vmcs_state[vcpu] == VS_NONE && curthread->t_preempt != 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

2775

vmx->vmcs_state[vcpu] = VS_LOADED;

usr/src/uts/intel/io/vmm/intel/vmx.c

2788

vmx_set_pcpu_defaults(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

280

SDT_PROBE_DEFINE3(vmm, vmx, exit, apicaccess,

usr/src/uts/intel/io/vmm/intel/vmx.c

2801

inject_state = vmx_inject_events(vmx, vcpu, rip);

usr/src/uts/intel/io/vmm/intel/vmx.c

2829

inject_state = vmx_inject_vlapic(vmx, vcpu, vlapic);

usr/src/uts/intel/io/vmm/intel/vmx.c

283

SDT_PROBE_DEFINE4(vmm, vmx, exit, apicwrite,

usr/src/uts/intel/io/vmm/intel/vmx.c

2836

if (vcpu_entry_bailout_checks(vmx->vm, vcpu, rip)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

2843

vm_exit_run_state(vmx->vm, vcpu, rip);

usr/src/uts/intel/io/vmm/intel/vmx.c

2851

if (vmx_inject_recheck(vmx, vcpu, inject_state)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

286

SDT_PROBE_DEFINE3(vmm, vmx, exit, xsetbv,

usr/src/uts/intel/io/vmm/intel/vmx.c

2875

launched = (vmx->vmcs_state[vcpu] & VS_LAUNCHED) != 0;

usr/src/uts/intel/io/vmm/intel/vmx.c

289

SDT_PROBE_DEFINE3(vmm, vmx, exit, monitor,

usr/src/uts/intel/io/vmm/intel/vmx.c

2892

vmexit->u.vmx.status = VM_FAIL_INVALID;

usr/src/uts/intel/io/vmm/intel/vmx.c

2906

if (vmx->eptgen[curcpu] != eptgen) {

usr/src/uts/intel/io/vmm/intel/vmx.c

2912

invept(1, vmx->eptp);

usr/src/uts/intel/io/vmm/intel/vmx.c

2913

vmx->eptgen[curcpu] = eptgen;

usr/src/uts/intel/io/vmm/intel/vmx.c

292

SDT_PROBE_DEFINE3(vmm, vmx, exit, mwait,

usr/src/uts/intel/io/vmm/intel/vmx.c

2920

rc = vmx_enter_guest(vmxctx, vmx, launched);

usr/src/uts/intel/io/vmm/intel/vmx.c

2925

vmx->vmcs_state[vcpu] |= VS_LAUNCHED;

usr/src/uts/intel/io/vmm/intel/vmx.c

2935

vmexit->u.vmx.exit_reason = exit_reason =

usr/src/uts/intel/io/vmm/intel/vmx.c

2937

vmexit->u.vmx.exit_qualification =

usr/src/uts/intel/io/vmm/intel/vmx.c

2940

vmx->state[vcpu].nextrip = rip;

usr/src/uts/intel/io/vmm/intel/vmx.c

2949

handled = vmx_exit_process(vmx, vcpu, vmexit);

usr/src/uts/intel/io/vmm/intel/vmx.c

295

SDT_PROBE_DEFINE3(vmm, vmx, exit, vminsn,

usr/src/uts/intel/io/vmm/intel/vmx.c

2965

vmx_msr_guest_exit(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

2967

VERIFY(vmx->vmcs_state[vcpu] != VS_NONE && curthread->t_preempt != 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

2968

vmx->vmcs_state[vcpu] = VS_NONE;

usr/src/uts/intel/io/vmm/intel/vmx.c

2977

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

298

SDT_PROBE_DEFINE4(vmm, vmx, exit, unknown,

usr/src/uts/intel/io/vmm/intel/vmx.c

2980

if (vmx_cap_en(vmx, VMX_CAP_APICV)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

2981

(void) vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE);

usr/src/uts/intel/io/vmm/intel/vmx.c

2982

kmem_free(vmx->apic_access_page, PAGESIZE);

usr/src/uts/intel/io/vmm/intel/vmx.c

2984

VERIFY3P(vmx->apic_access_page, ==, NULL);

usr/src/uts/intel/io/vmm/intel/vmx.c

2987

vmx_msr_bitmap_destroy(vmx);

usr/src/uts/intel/io/vmm/intel/vmx.c

2989

maxcpus = vm_get_maxcpus(vmx->vm);

usr/src/uts/intel/io/vmm/intel/vmx.c

2991

vpid_free(vmx->state[i].vpid);

usr/src/uts/intel/io/vmm/intel/vmx.c

2993

kmem_free(vmx, sizeof (*vmx));

usr/src/uts/intel/io/vmm/intel/vmx.c

3001

vmx_vmcs_access_ensure(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

3005

if (vcpu_is_running(vmx->vm, vcpu, &hostcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

301

SDT_PROBE_DEFINE4(vmm, vmx, exit, return,

usr/src/uts/intel/io/vmm/intel/vmx.c

3013

vmcs_load(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3019

vmx_vmcs_access_done(struct vmx *vmx, int vcpu)

usr/src/uts/intel/io/vmm/intel/vmx.c

3023

if (vcpu_is_running(vmx->vm, vcpu, &hostcpu)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3030

vmcs_clear(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

307

static void vmx_apply_tsc_adjust(struct vmx *, int);

usr/src/uts/intel/io/vmm/intel/vmx.c

3089

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3093

if ((regp = vmxctx_regptr(&vmx->ctx[vcpu], reg)) != NULL) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3098

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3129

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

313

vmx_allow_x2apic_msrs(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx.c

3137

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3141

if ((regp = vmxctx_regptr(&vmx->ctx[vcpu], reg)) != NULL) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3146

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3172

vmx_sync_efer_state(vmx, vcpu, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

318

guest_msr_ro(vmx, vcpuid, MSR_APIC_ID);

usr/src/uts/intel/io/vmm/intel/vmx.c

319

guest_msr_ro(vmx, vcpuid, MSR_APIC_VERSION);

usr/src/uts/intel/io/vmm/intel/vmx.c

320

guest_msr_ro(vmx, vcpuid, MSR_APIC_LDR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3201

vmx_invvpid(vmx, vcpu,

usr/src/uts/intel/io/vmm/intel/vmx.c

3202

vcpu_is_running(vmx->vm, vcpu, NULL));

usr/src/uts/intel/io/vmm/intel/vmx.c

321

guest_msr_ro(vmx, vcpuid, MSR_APIC_SVR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3214

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3222

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3225

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3237

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

324

guest_msr_ro(vmx, vcpuid, MSR_APIC_ISR0 + i);

usr/src/uts/intel/io/vmm/intel/vmx.c

3245

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3248

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

325

guest_msr_ro(vmx, vcpuid, MSR_APIC_TMR0 + i);

usr/src/uts/intel/io/vmm/intel/vmx.c

3258

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

326

guest_msr_ro(vmx, vcpuid, MSR_APIC_IRR0 + i);

usr/src/uts/intel/io/vmm/intel/vmx.c

3264

vmx_msr_ptr(struct vmx *vmx, int vcpu, uint32_t msr)

usr/src/uts/intel/io/vmm/intel/vmx.c

3266

uint64_t *guest_msrs = vmx->guest_msrs[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

3289

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

329

guest_msr_ro(vmx, vcpuid, MSR_APIC_ESR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3293

const uint64_t *msrp = vmx_msr_ptr(vmx, vcpu, msr);

usr/src/uts/intel/io/vmm/intel/vmx.c

330

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_TIMER);

usr/src/uts/intel/io/vmm/intel/vmx.c

3301

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3306

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

331

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_THERMAL);

usr/src/uts/intel/io/vmm/intel/vmx.c

3317

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

332

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_PCINT);

usr/src/uts/intel/io/vmm/intel/vmx.c

3321

uint64_t *msrp = vmx_msr_ptr(vmx, vcpu, msr);

usr/src/uts/intel/io/vmm/intel/vmx.c

3329

bool vmcs_loaded = vmx_vmcs_access_ensure(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

333

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_LINT0);

usr/src/uts/intel/io/vmm/intel/vmx.c

3334

vmx_sync_efer_state(vmx, vcpu, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3338

vmx_vmcs_access_done(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

334

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_LINT1);

usr/src/uts/intel/io/vmm/intel/vmx.c

3348

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

335

guest_msr_ro(vmx, vcpuid, MSR_APIC_LVT_ERROR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3354

vcap = vmx->cap[vcpu].set;

usr/src/uts/intel/io/vmm/intel/vmx.c

336

guest_msr_ro(vmx, vcpuid, MSR_APIC_ICR_TIMER);

usr/src/uts/intel/io/vmm/intel/vmx.c

337

guest_msr_ro(vmx, vcpuid, MSR_APIC_DCR_TIMER);

usr/src/uts/intel/io/vmm/intel/vmx.c

338

guest_msr_ro(vmx, vcpuid, MSR_APIC_ICR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3388

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3399

pptr = &vmx->cap[vcpu].proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

3407

pptr = &vmx->cap[vcpu].proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

3416

pptr = &vmx->cap[vcpu].proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

3425

pptr = &vmx->cap[vcpu].proc_ctls2;

usr/src/uts/intel/io/vmm/intel/vmx.c

3435

if (vmx->cap[vcpu].exc_bitmap != 0xffffffff) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3436

pptr = &vmx->cap[vcpu].exc_bitmap;

usr/src/uts/intel/io/vmm/intel/vmx.c

3456

vmcs_load(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3458

vmcs_clear(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

346

guest_msr_rw(vmx, vcpuid, MSR_APIC_TPR);

usr/src/uts/intel/io/vmm/intel/vmx.c

3468

vmx->cap[vcpu].set |= (1 << type);

usr/src/uts/intel/io/vmm/intel/vmx.c

347

guest_msr_rw(vmx, vcpuid, MSR_APIC_EOI);

usr/src/uts/intel/io/vmm/intel/vmx.c

3470

vmx->cap[vcpu].set &= ~(1 << type);

usr/src/uts/intel/io/vmm/intel/vmx.c

348

guest_msr_rw(vmx, vcpuid, MSR_APIC_SELF_IPI);

usr/src/uts/intel/io/vmm/intel/vmx.c

3488

struct vmx *vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3616

struct vmx *vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3621

vmx = ((struct vlapic_vtx *)vlapic)->vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3623

proc_ctls = vmx->cap[vcpuid].proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

3627

vmx->cap[vcpuid].proc_ctls = proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

3629

vmcs_load(vmx->vmcs_pa[vcpuid]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3631

vmcs_clear(vmx->vmcs_pa[vcpuid]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3637

struct vmx *vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3642

vmx = ((struct vlapic_vtx *)vlapic)->vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3644

proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;

usr/src/uts/intel/io/vmm/intel/vmx.c

3650

vmx->cap[vcpuid].proc_ctls2 = proc_ctls2;

usr/src/uts/intel/io/vmm/intel/vmx.c

3652

vmcs_load(vmx->vmcs_pa[vcpuid]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3654

vmcs_clear(vmx->vmcs_pa[vcpuid]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3656

vmx_allow_x2apic_msrs(vmx, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

3758

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3763

vlapic_vtx->pir_desc = &vmx->pir_desc[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx.c

3764

vlapic_vtx->vmx = vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

3767

vlapic->vm = vmx->vm;

usr/src/uts/intel/io/vmm/intel/vmx.c

3769

vlapic->apic_page = (struct LAPIC *)&vmx->apic_page[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx.c

3771

if (vmx_cap_en(vmx, VMX_CAP_TPR_SHADOW)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3774

if (vmx_cap_en(vmx, VMX_CAP_APICV)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3780

if (vmx_cap_en(vmx, VMX_CAP_APICV_PIR)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3800

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3802

VERIFY(vmx_vmcs_access_ensure(vmx, vcpuid));

usr/src/uts/intel/io/vmm/intel/vmx.c

3805

vmx_stash_intinfo(vmx, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

3813

vmx_clear_nmi_window_exiting(vmx, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

3814

vmx_clear_int_window_exiting(vmx, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

3816

vmx_vmcs_access_done(vmx, vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx.c

3822

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3824

if ((vmx->vmcs_state[vcpu] & VS_LOADED) != 0) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3825

vmcs_clear(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3826

vmx_msr_guest_exit(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3831

vmx->vmcs_state[vcpu] &= ~VS_LAUNCHED;

usr/src/uts/intel/io/vmm/intel/vmx.c

3840

struct vmx *vmx = arg;

usr/src/uts/intel/io/vmm/intel/vmx.c

3842

ASSERT0(vmx->vmcs_state[vcpu] & VS_LAUNCHED);

usr/src/uts/intel/io/vmm/intel/vmx.c

3844

if ((vmx->vmcs_state[vcpu] & VS_LOADED) != 0) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3845

vmx_msr_guest_enter(vmx, vcpu);

usr/src/uts/intel/io/vmm/intel/vmx.c

3846

vmcs_load(vmx->vmcs_pa[vcpu]);

usr/src/uts/intel/io/vmm/intel/vmx.c

690

struct vmx *vmx;

usr/src/uts/intel/io/vmm/intel/vmx.c

696

vmx = kmem_zalloc(sizeof (struct vmx), KM_SLEEP);

usr/src/uts/intel/io/vmm/intel/vmx.c

697

VERIFY3U((uintptr_t)vmx & PAGE_MASK, ==, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

699

vmx->vm = vm;

usr/src/uts/intel/io/vmm/intel/vmx.c

700

vmx->eptp = vmspace_table_root(vm_get_vmspace(vm));

usr/src/uts/intel/io/vmm/intel/vmx.c

711

hma_vmx_invept_allcpus((uintptr_t)vmx->eptp);

usr/src/uts/intel/io/vmm/intel/vmx.c

713

vmx_msr_bitmap_initialize(vmx);

usr/src/uts/intel/io/vmm/intel/vmx.c

722

vmx->vmx_caps = vmx_capabilities;

usr/src/uts/intel/io/vmm/intel/vmx.c

724

if (vmx_cap_en(vmx, VMX_CAP_TPR_SHADOW)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

729

if (vmx_cap_en(vmx, VMX_CAP_APICV)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

730

ASSERT(vmx_cap_en(vmx, VMX_CAP_TPR_SHADOW));

usr/src/uts/intel/io/vmm/intel/vmx.c

741

vmx->apic_access_page = kmem_zalloc(PAGESIZE, KM_SLEEP);

usr/src/uts/intel/io/vmm/intel/vmx.c

742

VERIFY3U((uintptr_t)vmx->apic_access_page & PAGEOFFSET, ==, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

743

apic_access_pa = vtophys(vmx->apic_access_page);

usr/src/uts/intel/io/vmm/intel/vmx.c

750

if (vmx_cap_en(vmx, VMX_CAP_APICV_PIR)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

751

ASSERT(vmx_cap_en(vmx, VMX_CAP_APICV));

usr/src/uts/intel/io/vmm/intel/vmx.c

779

vm_paddr_t msr_bitmap_pa = vtophys(vmx->msr_bitmap[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

780

vm_paddr_t apic_page_pa = vtophys(&vmx->apic_page[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

781

vm_paddr_t pir_desc_pa = vtophys(&vmx->pir_desc[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

783

vmx->vmcs_pa[i] = (uintptr_t)vtophys(&vmx->vmcs[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

784

vmcs_initialize(&vmx->vmcs[i], vmx->vmcs_pa[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

786

vmx_msr_guest_init(vmx, i);

usr/src/uts/intel/io/vmm/intel/vmx.c

788

vmcs_load(vmx->vmcs_pa[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

823

vmcs_write(VMCS_EPTP, vmx->eptp);

usr/src/uts/intel/io/vmm/intel/vmx.c

853

vmx->ctx[i].guest_dr6 = DBREG_DR6_RESERVED1;

usr/src/uts/intel/io/vmm/intel/vmx.c

856

if (vmx_cap_en(vmx, VMX_CAP_TPR_SHADOW)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

860

if (vmx_cap_en(vmx, VMX_CAP_APICV)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

867

if (vmx_cap_en(vmx, VMX_CAP_APICV_PIR)) {

usr/src/uts/intel/io/vmm/intel/vmx.c

883

vmcs_clear(vmx->vmcs_pa[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

885

vmx->cap[i].set = cap_defaults;

usr/src/uts/intel/io/vmm/intel/vmx.c

886

vmx->cap[i].proc_ctls = proc_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

887

vmx->cap[i].proc_ctls2 = proc2_ctls;

usr/src/uts/intel/io/vmm/intel/vmx.c

888

vmx->cap[i].exc_bitmap = exc_bitmap;

usr/src/uts/intel/io/vmm/intel/vmx.c

890

vmx->state[i].nextrip = ~0;

usr/src/uts/intel/io/vmm/intel/vmx.c

891

vmx->state[i].lastcpu = NOCPU;

usr/src/uts/intel/io/vmm/intel/vmx.c

892

vmx->state[i].vpid = vpid[i];

usr/src/uts/intel/io/vmm/intel/vmx.c

895

return (vmx);

usr/src/uts/intel/io/vmm/intel/vmx.c

940

vmx_invvpid(struct vmx *vmx, int vcpu, int running)

usr/src/uts/intel/io/vmm/intel/vmx.c

945

vmxstate = &vmx->state[vcpu];

usr/src/uts/intel/io/vmm/intel/vmx.c

968

vms = vm_get_vmspace(vmx->vm);

usr/src/uts/intel/io/vmm/intel/vmx.c

969

if (vmspace_table_gen(vms) == vmx->eptgen[curcpu]) {

usr/src/uts/intel/io/vmm/intel/vmx.c

978

vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_DONE, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

986

vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_SAVED, 1);

usr/src/uts/intel/io/vmm/intel/vmx.h

155

CTASSERT((offsetof(struct vmx, vmcs) & PAGE_MASK) == 0);

usr/src/uts/intel/io/vmm/intel/vmx.h

156

CTASSERT((offsetof(struct vmx, msr_bitmap) & PAGE_MASK) == 0);

usr/src/uts/intel/io/vmm/intel/vmx.h

157

CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0);

usr/src/uts/intel/io/vmm/intel/vmx.h

160

vmx_cap_en(const struct vmx *vmx, enum vmx_caps cap)

usr/src/uts/intel/io/vmm/intel/vmx.h

162

return ((vmx->vmx_caps & cap) == cap);

usr/src/uts/intel/io/vmm/intel/vmx.h

194

int vmx_enter_guest(struct vmxctx *ctx, struct vmx *vmx, int launched);

usr/src/uts/intel/io/vmm/intel/vmx.h

197

int vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

151

vmx_msr_bitmap_initialize(struct vmx *vmx)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

160

vmx->msr_bitmap[i] = bitmap;

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

165

vmx_msr_bitmap_destroy(struct vmx *vmx)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

168

VERIFY3P(vmx->msr_bitmap[i], !=, NULL);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

169

kmem_free(vmx->msr_bitmap[i], PAGESIZE);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

170

vmx->msr_bitmap[i] = NULL;

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

175

vmx_msr_bitmap_change_access(struct vmx *vmx, int vcpuid, uint_t msr, int acc)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

177

uint8_t *bitmap = vmx->msr_bitmap[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

336

vmx_msr_guest_init(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

338

uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

361

guest_msr_rw(vmx, vcpuid, MSR_GSBASE);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

362

guest_msr_rw(vmx, vcpuid, MSR_FSBASE);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

363

guest_msr_rw(vmx, vcpuid, MSR_SYSENTER_CS_MSR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

364

guest_msr_rw(vmx, vcpuid, MSR_SYSENTER_ESP_MSR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

365

guest_msr_rw(vmx, vcpuid, MSR_SYSENTER_EIP_MSR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

366

guest_msr_rw(vmx, vcpuid, MSR_EFER);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

367

guest_msr_ro(vmx, vcpuid, MSR_TSC);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

373

guest_msr_rw(vmx, vcpuid, MSR_LSTAR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

374

guest_msr_rw(vmx, vcpuid, MSR_CSTAR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

375

guest_msr_rw(vmx, vcpuid, MSR_STAR);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

376

guest_msr_rw(vmx, vcpuid, MSR_SF_MASK);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

377

guest_msr_rw(vmx, vcpuid, MSR_KGSBASE);

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

393

vmx_msr_guest_enter(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

395

uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

396

uint64_t *host_msrs = vmx->host_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

413

vmx_msr_guest_exit(struct vmx *vmx, int vcpuid)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

415

uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

416

uint64_t *host_msrs = vmx->host_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

435

vmx_rdmsr(struct vmx *vmx, int vcpuid, uint32_t num, uint64_t *val)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

437

const uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

468

vmx_wrmsr(struct vmx *vmx, int vcpuid, uint32_t num, uint64_t val)

usr/src/uts/intel/io/vmm/intel/vmx_msr.c

470

uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

48

void vmx_msr_guest_init(struct vmx *vmx, int vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

49

void vmx_msr_guest_enter(struct vmx *vmx, int vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

50

void vmx_msr_guest_exit(struct vmx *vmx, int vcpuid);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

51

vm_msr_result_t vmx_rdmsr(struct vmx *, int, uint32_t, uint64_t *);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

52

vm_msr_result_t vmx_wrmsr(struct vmx *, int, uint32_t, uint64_t);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

72

void vmx_msr_bitmap_initialize(struct vmx *);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

73

void vmx_msr_bitmap_destroy(struct vmx *);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

74

void vmx_msr_bitmap_change_access(struct vmx *, int, uint_t, int);

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

76

#define guest_msr_rw(vmx, vcpuid, msr) \

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

77

vmx_msr_bitmap_change_access((vmx), (vcpuid), (msr), MSR_BITMAP_ACCESS_RW)

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

79

#define guest_msr_ro(vmx, vcpuid, msr) \

usr/src/uts/intel/io/vmm/intel/vmx_msr.h

80

vmx_msr_bitmap_change_access((vmx), (vcpuid), (msr), MSR_BITMAP_ACCESS_READ)

usr/src/uts/intel/os/hma.c

107

struct hma_vmx_cpu vmx;

usr/src/uts/intel/os/hma.c

256

return (&hma_cpu[id].hc_u.vmx);

usr/src/uts/intel/sys/vmm.h

354

} vmx;