vmcs_write - Illumos

usr/src/uts/intel/io/vmm/intel/vmcs.h

69

void vmcs_write(uint32_t encoding, uint64_t val);

usr/src/uts/intel/io/vmm/intel/vmx.c

1023

vmcs_write(VMCS_HOST_IA32_SYSENTER_ESP, rdmsr(MSR_SYSENTER_ESP_MSR));

usr/src/uts/intel/io/vmm/intel/vmx.c

1040

vmcs_write(VMCS_HOST_IDTR_BASE, vmm_get_host_idtrbase());

usr/src/uts/intel/io/vmm/intel/vmx.c

1041

vmcs_write(VMCS_HOST_TR_BASE, vmm_get_host_trbase());

usr/src/uts/intel/io/vmm/intel/vmx.c

1042

vmcs_write(VMCS_HOST_GDTR_BASE, vmm_get_host_gdtrbase());

usr/src/uts/intel/io/vmm/intel/vmx.c

1043

vmcs_write(VMCS_HOST_GS_BASE, vmm_get_host_gsbase());

usr/src/uts/intel/io/vmm/intel/vmx.c

1059

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1068

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1082

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1090

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

1108

vmcs_write(VMCS_TSC_OFFSET, offset);

usr/src/uts/intel/io/vmm/intel/vmx.c

1172

vmcs_write(VMCS_ENTRY_INTR_INFO, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

1173

vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

1203

vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR,

usr/src/uts/intel/io/vmm/intel/vmx.c

1206

vmcs_write(VMCS_ENTRY_INTR_INFO, inject);

usr/src/uts/intel/io/vmm/intel/vmx.c

1224

vmcs_write(VMCS_ENTRY_INTR_INFO,

usr/src/uts/intel/io/vmm/intel/vmx.c

1255

vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);

usr/src/uts/intel/io/vmm/intel/vmx.c

1318

vmcs_write(VMCS_ENTRY_INTR_INFO,

usr/src/uts/intel/io/vmm/intel/vmx.c

1364

vmcs_write(VMCS_GUEST_INTR_STATUS, status_new);

usr/src/uts/intel/io/vmm/intel/vmx.c

1390

vmcs_write(VMCS_ENTRY_INTR_INFO,

usr/src/uts/intel/io/vmm/intel/vmx.c

1455

vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);

usr/src/uts/intel/io/vmm/intel/vmx.c

1465

vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);

usr/src/uts/intel/io/vmm/intel/vmx.c

1621

vmcs_write(VMCS_GUEST_RSP, regval);

usr/src/uts/intel/io/vmm/intel/vmx.c

1677

vmcs_write(VMCS_ENTRY_CTLS, ctrl);

usr/src/uts/intel/io/vmm/intel/vmx.c

1691

vmcs_write(VMCS_CR0_SHADOW, regval);

usr/src/uts/intel/io/vmm/intel/vmx.c

1703

vmcs_write(VMCS_GUEST_CR0, crval);

usr/src/uts/intel/io/vmm/intel/vmx.c

1712

vmcs_write(VMCS_GUEST_IA32_EFER, efer);

usr/src/uts/intel/io/vmm/intel/vmx.c

1731

vmcs_write(VMCS_CR4_SHADOW, regval);

usr/src/uts/intel/io/vmm/intel/vmx.c

1735

vmcs_write(VMCS_GUEST_CR4, crval);

usr/src/uts/intel/io/vmm/intel/vmx.c

2262

vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);

usr/src/uts/intel/io/vmm/intel/vmx.c

2473

vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);

usr/src/uts/intel/io/vmm/intel/vmx.c

2602

vmcs_write(VMCS_GUEST_RIP, vmexit->rip);

usr/src/uts/intel/io/vmm/intel/vmx.c

2785

vmcs_write(VMCS_HOST_CR3, rcr3());

usr/src/uts/intel/io/vmm/intel/vmx.c

2787

vmcs_write(VMCS_GUEST_RIP, rip);

usr/src/uts/intel/io/vmm/intel/vmx.c

3161

vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);

usr/src/uts/intel/io/vmm/intel/vmx.c

3171

vmcs_write(encoding, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3184

vmcs_write(VMCS_CR0_SHADOW, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3185

vmcs_write(encoding, vmx_fix_cr0(val));

usr/src/uts/intel/io/vmm/intel/vmx.c

3189

vmcs_write(VMCS_CR4_SHADOW, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3190

vmcs_write(encoding, vmx_fix_cr4(val));

usr/src/uts/intel/io/vmm/intel/vmx.c

3193

vmcs_write(encoding, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3208

vmcs_write(encoding, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3251

vmcs_write(base, desc->base);

usr/src/uts/intel/io/vmm/intel/vmx.c

3252

vmcs_write(limit, desc->limit);

usr/src/uts/intel/io/vmm/intel/vmx.c

3254

vmcs_write(access, desc->access);

usr/src/uts/intel/io/vmm/intel/vmx.c

3331

vmcs_write(vmcs_enc, val);

usr/src/uts/intel/io/vmm/intel/vmx.c

3457

vmcs_write(reg, baseval);

usr/src/uts/intel/io/vmm/intel/vmx.c

3606

vmcs_write(VMCS_EOI_EXIT0, ((uint64_t)tmrs[1] << 32) | tmrs[0]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3607

vmcs_write(VMCS_EOI_EXIT1, ((uint64_t)tmrs[3] << 32) | tmrs[2]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3608

vmcs_write(VMCS_EOI_EXIT2, ((uint64_t)tmrs[5] << 32) | tmrs[4]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3609

vmcs_write(VMCS_EOI_EXIT3, ((uint64_t)tmrs[7] << 32) | tmrs[6]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3630

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

3653

vmcs_write(VMCS_SEC_PROC_BASED_CTLS, proc_ctls2);

usr/src/uts/intel/io/vmm/intel/vmx.c

3741

vmcs_write(VMCS_TPR_THRESHOLD, vlapic_get_cr8(vlapic));

usr/src/uts/intel/io/vmm/intel/vmx.c

790

vmcs_write(VMCS_HOST_IA32_PAT, vmm_get_host_pat());

usr/src/uts/intel/io/vmm/intel/vmx.c

791

vmcs_write(VMCS_HOST_IA32_EFER, vmm_get_host_efer());

usr/src/uts/intel/io/vmm/intel/vmx.c

794

vmcs_write(VMCS_HOST_CR0, vmm_get_host_cr0());

usr/src/uts/intel/io/vmm/intel/vmx.c

795

vmcs_write(VMCS_HOST_CR4, vmm_get_host_cr4() | CR4_VMXE);

usr/src/uts/intel/io/vmm/intel/vmx.c

798

vmcs_write(VMCS_HOST_CS_SELECTOR, vmm_get_host_codesel());

usr/src/uts/intel/io/vmm/intel/vmx.c

800

vmcs_write(VMCS_HOST_ES_SELECTOR, datasel);

usr/src/uts/intel/io/vmm/intel/vmx.c

801

vmcs_write(VMCS_HOST_SS_SELECTOR, datasel);

usr/src/uts/intel/io/vmm/intel/vmx.c

802

vmcs_write(VMCS_HOST_DS_SELECTOR, datasel);

usr/src/uts/intel/io/vmm/intel/vmx.c

804

vmcs_write(VMCS_HOST_FS_SELECTOR, vmm_get_host_fssel());

usr/src/uts/intel/io/vmm/intel/vmx.c

805

vmcs_write(VMCS_HOST_GS_SELECTOR, vmm_get_host_gssel());

usr/src/uts/intel/io/vmm/intel/vmx.c

806

vmcs_write(VMCS_HOST_TR_SELECTOR, vmm_get_host_tsssel());

usr/src/uts/intel/io/vmm/intel/vmx.c

813

vmcs_write(VMCS_HOST_IA32_SYSENTER_CS, KCS_SEL);

usr/src/uts/intel/io/vmm/intel/vmx.c

814

vmcs_write(VMCS_HOST_IA32_SYSENTER_EIP,

usr/src/uts/intel/io/vmm/intel/vmx.c

818

vmcs_write(VMCS_HOST_RIP, (uint64_t)vmx_exit_guest);

usr/src/uts/intel/io/vmm/intel/vmx.c

821

vmcs_write(VMCS_LINK_POINTER, ~0);

usr/src/uts/intel/io/vmm/intel/vmx.c

823

vmcs_write(VMCS_EPTP, vmx->eptp);

usr/src/uts/intel/io/vmm/intel/vmx.c

824

vmcs_write(VMCS_PIN_BASED_CTLS, pin_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

825

vmcs_write(VMCS_PRI_PROC_BASED_CTLS, proc_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

830

vmcs_write(VMCS_SEC_PROC_BASED_CTLS, use_proc2_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

832

vmcs_write(VMCS_EXIT_CTLS, exit_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

833

vmcs_write(VMCS_ENTRY_CTLS, entry_ctls);

usr/src/uts/intel/io/vmm/intel/vmx.c

834

vmcs_write(VMCS_MSR_BITMAP, msr_bitmap_pa);

usr/src/uts/intel/io/vmm/intel/vmx.c

835

vmcs_write(VMCS_VPID, vpid[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

838

vmcs_write(VMCS_ENTRY_MSR_LOAD,

usr/src/uts/intel/io/vmm/intel/vmx.c

840

vmcs_write(VMCS_ENTRY_MSR_LOAD_COUNT,

usr/src/uts/intel/io/vmm/intel/vmx.c

842

vmcs_write(VMCS_EXIT_MSR_STORE, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

843

vmcs_write(VMCS_EXIT_MSR_STORE_COUNT, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

851

vmcs_write(VMCS_EXCEPTION_BITMAP, exc_bitmap);

usr/src/uts/intel/io/vmm/intel/vmx.c

854

vmcs_write(VMCS_GUEST_DR7, DBREG_DR7_RESERVED1);

usr/src/uts/intel/io/vmm/intel/vmx.c

857

vmcs_write(VMCS_VIRTUAL_APIC, apic_page_pa);

usr/src/uts/intel/io/vmm/intel/vmx.c

861

vmcs_write(VMCS_APIC_ACCESS, apic_access_pa);

usr/src/uts/intel/io/vmm/intel/vmx.c

862

vmcs_write(VMCS_EOI_EXIT0, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

863

vmcs_write(VMCS_EOI_EXIT1, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

864

vmcs_write(VMCS_EOI_EXIT2, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

865

vmcs_write(VMCS_EOI_EXIT3, 0);

usr/src/uts/intel/io/vmm/intel/vmx.c

868

vmcs_write(VMCS_PIR_VECTOR, pirvec);

usr/src/uts/intel/io/vmm/intel/vmx.c

869

vmcs_write(VMCS_PIR_DESC, pir_desc_pa);

usr/src/uts/intel/io/vmm/intel/vmx.c

878

vmcs_write(VMCS_CR0_MASK, cr0_ones_mask | cr0_zeros_mask);

usr/src/uts/intel/io/vmm/intel/vmx.c

879

vmcs_write(VMCS_CR0_SHADOW, 0x60000010);

usr/src/uts/intel/io/vmm/intel/vmx.c

880

vmcs_write(VMCS_CR4_MASK, cr4_ones_mask | cr4_zeros_mask);

usr/src/uts/intel/io/vmm/intel/vmx.c

881

vmcs_write(VMCS_CR4_SHADOW, 0);