vf_number
lm_igu_sb->vf_number = fid & IGU_FID_VF_NUM_MASK;
if ((lm_igu_sb->vf_number >= pdev->hw_info.sriov_info.first_vf_in_pf)
&& (lm_igu_sb->vf_number < (pdev->hw_info.sriov_info.first_vf_in_pf + pdev->hw_info.sriov_info.total_vfs)))
lm_igu_sb->vf_number = abs_vf_id;
lm_igu_sb->vf_number = lm_igu_sb->vector_number = 0xFF;
lm_igu_sb->vf_number = lm_igu_sb->vector_number = 0xFF;
u8_t vf_number;
u32 vf_number;
static s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number)
if (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFREQ_VF1 << vf_number)) {
static s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number)
if (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFACK_VF1 << vf_number)) {
static s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)
if (vflre & (1 << vf_number)) {
E1000_WRITE_REG(hw, E1000_VFLRE, (1 << vf_number));
static s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number)
E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number),
p2v_mailbox = E1000_READ_REG(hw, E1000_P2VMAILBOX(vf_number));
u16 vf_number)
ret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);
e1000_check_for_msg_pf(hw, vf_number);
e1000_check_for_ack_pf(hw, vf_number);
E1000_WRITE_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i, msg[i]);
E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS);
u16 vf_number)
ret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);
msg[i] = E1000_READ_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i);
E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);
u32 vf_number;
mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
if (vf_number > 63)
offset = queue_count * vf_number + i;
s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number);
s32 (*check_for_msg)(struct ixgbe_hw *hw, u16 vf_number);
s32 (*check_for_ack)(struct ixgbe_hw *hw, u16 vf_number);
s32 (*check_for_rst)(struct ixgbe_hw *hw, u16 vf_number);
s32 (*clear)(struct ixgbe_hw *hw, u16 vf_number);
#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
u8 pf_id, u16 vf_number, u8 vf_valid)
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
u16 vf_number, u8 vf_valid)
vf_number, vf_valid);
uint32_t vf_number:16; /* word 6 */
uint32_t vf_number:16; /* word 6 */