vBIT
#define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2)
#define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
#define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
#define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16)
#define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6)
#define XGE_HAL_TXD_SET_MARKER vBIT(0x6,0,4)
#define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
#define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
#define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2)
#define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
#define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
#define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
#define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
#define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
#define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
#define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
#define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
#define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4)
#define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16)
#define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17)
#define XGE_HAL_PCI_INFO vBIT(0xF,0,4)
#define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
#define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32)
#define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32)
#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3)
#define XGE_HAL_XMSI_NO(val) vBIT(val,26,6)
#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8)
#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8)
#define XGE_HAL_STAT_BYTE_CNT(n) vBIT(n, 4, 12)
#define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32)
#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16)
#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5)
#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5)
#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16)
#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4)
#define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2)
#define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
#define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
#define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
#define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3)
#define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3)
#define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
#define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
#define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
#define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
#define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
#define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
#define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8)
#define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8)
#define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8)
#define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
#define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
#define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
#define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
#define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
#define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
#define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
#define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
#define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
#define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
#define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
#define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
#define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
#define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
#define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
#define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
#define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
#define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
#define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
#define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
#define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
#define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
#define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
#define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
#define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
#define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
#define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
#define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
#define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
#define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
#define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8)
#define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
#define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
#define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
#define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
#define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
#define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
#define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
#define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8)
#define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
#define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8)
#define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8)
#define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
#define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
#define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
#define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2)
#define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2)
#define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
#define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
#define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1)
#define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1)
#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
#define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8)
#define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
#define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16)
#define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
#define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
#define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
#define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
#define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
#define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
#define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
#define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
#define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
#define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
#define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
#define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
#define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3)
#define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
#define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
#define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
#define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
#define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8)
#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
#define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4)
#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8)
#define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
#define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3)
#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3)
#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
#define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32)
#define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32)
#define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
#define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32)
#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
(u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8)
#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8)
#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
(int)((Control_2 & vBIT(0xFF,8,8))>>48)
(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16)
#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16)
#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16)
#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16)
(int)((Control_3 & vBIT(0xFFFF,32,16))>>16)
(int)((Control_3 & vBIT(0xFFFF,48,16)))
#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
(u8)((Control_1 & vBIT(0xF,20,4))>>40)
#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16)
#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2)
#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8)
val64 = vBIT(port->num,8,16) |
vBIT(rnum,37,3) | BIT(63);
val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8);
spdm_line_arr[0] = vBIT(l4_sp,0,16) |
vBIT(l4_dp,16,32) |
vBIT(tgt_queue,53,3) |
vBIT(is_tcp,59,1) |
vBIT(is_ipv4,63,1);
spdm_line_arr[1] = vBIT(src_ip->ipv4.addr,0,32) |
vBIT(dst_ip->ipv4.addr,32,32);
spdm_line_arr[7] = vBIT(jhash_value,0,32) |
u64 mask = vBIT(0xff,(loc*8),8);
vBIT((hldev->config.fifo.queue[i].max-1),
13) | vBIT(priority, (((reg_half)*32) + 5), 3);
val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
val64 |= vBIT(hldev->config.ring.queue[i].priority,
val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);