ural_write
ural_write(sc, RAL_TXRX_CSR19, 0);
ural_write(sc, RAL_TXRX_CSR18, tmp);
ural_write(sc, RAL_TXRX_CSR20, tmp);
ural_write(sc, RAL_TXRX_CSR19, tmp);
ural_write(sc, RAL_MAC_CSR10, slottime);
ural_write(sc, RAL_MAC_CSR11, sifs);
ural_write(sc, RAL_MAC_CSR12, eifs);
ural_write(sc, RAL_TXRX_CSR10, tmp);
ural_write(sc, RAL_TXRX_CSR11, 0x3);
ural_write(sc, RAL_TXRX_CSR11, 0x150);
ural_write(sc, RAL_TXRX_CSR11, 0x15f);
ural_write(sc, RAL_MAC_CSR5, tmp);
ural_write(sc, RAL_MAC_CSR6, tmp);
ural_write(sc, RAL_MAC_CSR7, tmp);
ural_write(sc, RAL_MAC_CSR2, tmp);
ural_write(sc, RAL_MAC_CSR3, tmp);
ural_write(sc, RAL_MAC_CSR4, tmp);
ural_write(sc, RAL_TXRX_CSR2, tmp);
ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
ural_write(sc, RAL_TXRX_CSR19, 0);
ural_write(sc, RAL_MAC_CSR20, 0);
ural_write(sc, RAL_MAC_CSR20, 1);
ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
ural_write(sc, RAL_MAC_CSR1, 0);
ural_write(sc, 0x308, 0x00f0); /* magic */
ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
ural_write(sc, RAL_TXRX_CSR11, 0x15f);
ural_write(sc, RAL_TXRX_CSR2, tmp);
ural_write(sc, RAL_PHY_CSR7, tmp);
ural_write(sc, RAL_PHY_CSR7, val);
ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
ural_write(sc, RAL_PHY_CSR10, tmp >> 16);