tw32
tw32(MAC_TX_AUTO_NEG, 0);
tw32(MAC_TX_AUTO_NEG, ap->txconfig);
tw32(MAC_TX_AUTO_NEG, ap->txconfig);
tw32(reg, val);
tw32(MAC_TX_AUTO_NEG, 0);
tw32(MAC_TX_LENGTHS,
tw32(MAC_TX_LENGTHS,
tw32(ofs, val);
tw32(TG3PCI_MISC_HOST_CTRL,
tw32(FTQ_RESET, 0xffffffff);
tw32(FTQ_RESET, 0x00000000);
tw32(NVRAM_SWARB, SWARB_REQ_SET1);
tw32(GRC_MISC_CFG, val);
tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
tw32(GRC_RX_CPU_EVENT, val);
tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
tw32(MAC_TX_BACKOFF_SEED, addr_high);
tw32(_table[0], _table[1]); \
tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
tw32(GRC_MODE, tp->grc_mode); /* Redundant? */
tw32(TG3PCI_PCISTATE, val);
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
tw32(GRC_MODE,
tw32(GRC_MISC_CFG,
tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
tw32(BUFMGR_MB_RDMA_LOW_WATER,
tw32(BUFMGR_MB_MACRX_LOW_WATER,
tw32(BUFMGR_MB_HIGH_WATER,
tw32(BUFMGR_MB_RDMA_LOW_WATER,
tw32(BUFMGR_MB_MACRX_LOW_WATER,
tw32(BUFMGR_MB_HIGH_WATER,
tw32(BUFMGR_DMA_LOW_WATER,
tw32(BUFMGR_DMA_HIGH_WATER,
tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
tw32(FTQ_RESET, 0xffffffff);
tw32(FTQ_RESET, 0x00000000);
tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
tw32(HOSTCC_MODE, 0);
tw32(TG3PCI_X_CAPS, val);
tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
tw32(MAC_LED_CTRL, 0);
tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
tw32(MAC_SERDES_CFG, 0x616000);
tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
case 16: tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
case 15: tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
case 14: tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
case 13: tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
case 12: tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
case 11: tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
case 10: tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
case 9: tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
case 8: tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
case 7: tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
case 6: tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
case 5: tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
tw32(GRC_EEPROM_ADDR,
tw32(NVRAM_CFG1, nvcfg1);
tw32(GRC_EEPROM_ADDR,
tw32(NVRAM_SWARB, SWARB_REQ_SET1);
tw32(NVRAM_ADDR, offset);
tw32(NVRAM_CMD,
tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
tw32(NVRAM_SWARB, 0x20);
tw32(GRC_MODE, tp->grc_mode);
tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
tw32(TG3PCI_CLOCK_CTRL, 0);
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);