tr32
tr32(reg);
(tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
tr32(reg);
if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
if ((tr32(MAC_STATUS) &
(tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
if ((tr32(MAC_STATUS) &
if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
val = tr32(ofs);
tr32(ofs);
val = tr32(ofs);
if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
tr32(MAC_TX_MODE));
if (tr32(NVRAM_SWARB) & SWARB_GNT1)
clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
val = tr32(GRC_RX_CPU_EVENT);
if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
val = tr32(TG3PCI_PCISTATE);
if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
if (tr32(FTQ_RESET) == 0x00000000)
frame_val = tr32(MAC_MI_COM);
frame_val = tr32(MAC_MI_COM);
if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
tr32(MAILBOX_INTERRUPT_0);
((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
val = tr32(TG3PCI_X_CAPS);
tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
uint32_t nvcfg1 = tr32(NVRAM_CFG1);
tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
tmp = tr32(GRC_EEPROM_ADDR);
*val = tr32(GRC_EEPROM_DATA);
if (tr32(NVRAM_SWARB) & SWARB_GNT1)
frame_val = tr32(MAC_MI_COM);
!(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
*val = bswap_32(tr32(NVRAM_RDDATA));
frame_val = tr32(MAC_MI_COM);
grc_misc_cfg = tr32(GRC_MISC_CFG);
hi = tr32(MAC_ADDR_0_HIGH);
lo = tr32(MAC_ADDR_0_LOW);
uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
mac_stat = tr32(MAC_STATUS);
tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);