t4_write_reg
t4_write_reg(adap, mem_base + offset,
t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
t4_write_reg(adapter, a_port_cfg,
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, window),
t4_write_reg(adap, port_base_addr + i, 0);
t4_write_reg(adap, port_base_addr + i, 0);
t4_write_reg(adap,
t4_write_reg(adap,
t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
t4_write_reg(adapter, addr, v | val);
t4_write_reg(adap, addr_reg, start_idx);
t4_write_reg(adap, addr_reg, start_idx++);
t4_write_reg(adap, data_reg, *vals++);
t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
t4_write_reg(adapter, A_SF_OP,
t4_write_reg(adapter, A_SF_DATA, val);
t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
t4_write_reg(adapter, reg, status);
t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE,
t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
t4_write_reg(adapter, addr, v);
t4_write_reg(adapter, A_MA_INT_CAUSE, status);
t4_write_reg(adap, int_cause_reg, v);
t4_write_reg(adapter, A_PL_INT_ENABLE, 0);
t4_write_reg(adapter, A_PL_INT_CAUSE, raw_cause & GLBL_INTR_MASK);
t4_write_reg(adapter, A_PL_INT_ENABLE, enable);
t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
t4_write_reg(adap, ctl_reg,
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
t4_write_reg(adap, A_TP_MTU_TABLE,
t4_write_reg(adap, A_TP_CCTRL_TABLE,
t4_write_reg(adap, A_TP_PIO_ADDR, addr);
t4_write_reg(adap, A_TP_PIO_DATA, val);
t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
t4_write_reg(adap, data_reg, tp->data[i]);
t4_write_reg(adap, mask_reg, ~tp->mask[i]);
t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
t4_write_reg(adap, ctl_reg,
t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
t4_write_reg(adap,
t4_write_reg(adap, mem_base + offset,
t4_write_reg(adap,
t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
void t4_write_reg(struct adapter *, uint32_t, uint32_t);
t4_write_reg(padap, A_CIM_HOST_ACC_CTRL, addr);
t4_write_reg(padap, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
t4_write_reg(padap, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
t4_write_reg(padap, A_LE_DB_DBGI_REQ_DATA + (i << 2), 0);
t4_write_reg(padap, A_LE_DB_DBGI_REQ_TCAM_CMD, val);
t4_write_reg(padap, A_LE_DB_DBGI_CONFIG, val);
t4_write_reg(padap, A_SGE_DEBUG_INDEX, (u32)i);
t4_write_reg(sc, r.reg, r.value);
t4_write_reg(sc, mw_base + off + i, *cfdata++);
t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0),
t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1),
t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2),
t4_write_reg(sc, reg, start | pf);
t4_write_reg(sc, A_SGE_STAT_CFG,
t4_write_reg(sc, A_TP_SHIFT_CNT,
t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
t4_write_reg(sc, A_PL_RST, F_PIORSTMODE | F_PIORST);
t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, rx_buf_size);
t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD,
t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1,
t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3,
t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5,
t4_write_reg(iq->adapter, MYPF_REG(A_SGE_PF_GTS), value);
t4_write_reg(iq->adapter, MYPF_REG(A_SGE_PF_GTS), value);
t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);