Symbol: t4_read_reg
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10005
u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1004
(__force __le32)t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10190
t4_read_reg(adapter, a_port_cfg)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10311
t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10371
hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10380
qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10382
qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10400
v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10456
v = t4_read_reg(adap, A_TP_OUT_CONFIG);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1046
edc_size = G_EDRAM0_SIZE(t4_read_reg(adap, A_MA_EDRAM0_BAR));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1052
mc_size = G_EXT_MEM0_SIZE(t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10921
v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10930
v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
10973
*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11002
v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11016
*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11036
if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11044
*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11063
if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11165
cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11170
val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11254
idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11255
idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11307
debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11311
debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
11381
v = t4_read_reg(adap, A_TP_PACE_TABLE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1161
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, window));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
12134
*data++ = t4_read_reg(adap, i);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
149
u32 val = t4_read_reg(adapter, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
183
u32 v = t4_read_reg(adapter, addr) & ~mask;
usr/src/uts/common/io/cxgbe/common/t4_hw.c
186
(void) t4_read_reg(adapter, addr); /* flush */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
207
*vals++ = t4_read_reg(adap, data_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
257
*val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
289
pcie_fw = t4_read_reg(adap, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3029
*bufp++ = t4_read_reg(adap, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3532
if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3538
*valp = t4_read_reg(adapter, A_SF_DATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3559
if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4543
cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4547
val = t4_read_reg(adap, A_CIM_DEBUGSTS);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4559
*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4560
*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4575
cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4584
*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4585
*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4599
j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4602
*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4634
unsigned int status = t4_read_reg(adapter, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
482
pcie_fw = t4_read_reg(adap, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4843
perr = t4_read_reg(adapter, A_SGE_INT_CAUSE1);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4848
perr = t4_read_reg(adapter, A_SGE_INT_CAUSE2);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4854
perr = t4_read_reg(adapter, A_SGE_INT_CAUSE5);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4869
err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4937
fw_err = t4_read_reg(adapter, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4947
val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
516
ctl = t4_read_reg(adap, ctl_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5173
t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5206
v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5211
u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5235
u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5240
t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5244
t4_read_reg(adapter,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5248
v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5303
v = t4_read_reg(adap, int_cause_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5400
u32 raw_cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5401
u32 enable = t4_read_reg(adapter, A_PL_INT_ENABLE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5409
(void)t4_read_reg(adapter, A_PL_INT_ENABLE); /* flush */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5465
(void)t4_read_reg(adapter, A_PL_INT_ENABLE); /* flush */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5485
u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5515
u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
568
(void) t4_read_reg(adap, ctl_reg); /* flush write */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
575
!((pcie_fw = t4_read_reg(adap, A_PCIE_FW)) & F_PCIE_FW_ERR) &&
usr/src/uts/common/io/cxgbe/common/t4_hw.c
585
v = t4_read_reg(adap, ctl_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5904
u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
5986
vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6205
v = t4_read_reg(adap, A_TP_MTU_TABLE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6228
incr[mtu][w] = (u16)t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6246
val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6371
v = t4_read_reg(adap, A_TP_TX_TRATE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6379
v = t4_read_reg(adap, A_TP_TX_ORATE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6421
cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6486
ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6487
ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6508
tp->mask[i] = ~t4_read_reg(adap, mask_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6509
tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6525
u32 tcb_base = t4_read_reg(adap, A_TP_CMM_TCB_BASE);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6556
cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6583
cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6610
nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6649
nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6707
unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6740
unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
682
pcie_fw = t4_read_reg(adap, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
6845
u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
693
ctl = t4_read_reg(adap, ctl_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7249
sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7364
if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
737
t4_read_reg(adap, ctl_reg); /* flush write */
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7414
pcie_fw = t4_read_reg(adap, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
744
!((pcie_fw = t4_read_reg(adap, A_PCIE_FW)) & F_PCIE_FW_ERR) &&
usr/src/uts/common/io/cxgbe/common/t4_hw.c
747
v = t4_read_reg(adap, ctl_reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7598
if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7704
sge_control = t4_read_reg(adap, A_SGE_CONTROL);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7730
sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7892
(t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align-1)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7895
(t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align-1)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
824
t4_read_reg(adap, edc_ecc_err_addr_reg));
usr/src/uts/common/io/cxgbe/common/t4_hw.c
894
mem_reg = t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
924
t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
963
*buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
9820
whoami = t4_read_reg(adapter, A_PL_WHOAMI);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
9825
whoami = t4_read_reg(adapter, A_PL_WHOAMI);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
983
t4_read_reg(adap,
usr/src/uts/common/io/cxgbe/t4nex/adapter.h
658
uint32_t t4_read_reg(struct adapter *, uint32_t);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1000
(md++)->base = t4_read_reg(padap, A_TP_CMM_MM_TX_FLST_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1001
(md++)->base = t4_read_reg(padap, A_TP_CMM_MM_PS_FLST_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1004
md->base = t4_read_reg(padap, A_TP_PMM_TX_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1006
t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1008
G_PMTXMAXPAGE(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1013
md->base = t4_read_reg(padap, A_TP_PMM_RX_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1015
t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1017
G_PMRXMAXPAGE(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1021
if (t4_read_reg(padap, A_LE_DB_CONFIG) & F_HASHEN) {
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1023
hi = t4_read_reg(padap, A_LE_DB_TID_HASHBASE) / 4;
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1024
md->base = t4_read_reg(padap, A_LE_DB_HASH_TID_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1026
hi = t4_read_reg(padap, A_LE_DB_HASH_TID_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1027
md->base = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1038
md->base = t4_read_reg(padap, A_ULP_ ## reg ## _LLIMIT);\
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1039
(md++)->limit = t4_read_reg(padap, A_ULP_ ## reg ## _ULIMIT);\
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1054
u32 sge_ctrl = t4_read_reg(padap, A_SGE_CONTROL2);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1055
u32 fifo_size = t4_read_reg(padap, A_SGE_DBVFIFO_SIZE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1063
md->base = G_BASEADDR(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1071
md->base = t4_read_reg(padap, A_ULP_RX_CTX_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1074
md->base = t4_read_reg(padap, A_ULP_TX_ERR_TABLE_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1101
lo = t4_read_reg(padap, A_CIM_SDRAM_BASE_ADDR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1102
hi = t4_read_reg(padap, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1106
lo = t4_read_reg(padap, A_CIM_EXTMEM2_BASE_ADDR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1107
hi = t4_read_reg(padap, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1111
lo = t4_read_reg(padap, A_TP_PMM_RX_MAX_PAGE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1114
t4_read_reg(padap, A_TP_PMM_RX_PAGE_SIZE) >> 10;
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1117
lo = t4_read_reg(padap, A_TP_PMM_TX_MAX_PAGE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1118
hi = t4_read_reg(padap, A_TP_PMM_TX_PAGE_SIZE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1128
lo = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1131
lo = t4_read_reg(padap, A_MPS_RX_PG_RSV0 + i * 4);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1145
lo = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1148
lo = t4_read_reg(padap, A_MPS_RX_PG_RSV4 + i * 4);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1302
clk_info_buff->res = t4_read_reg(padap, A_TP_TIMER_RESOLUTION);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1309
t4_read_reg(padap, A_TP_DACK_TIMER);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1312
tp_tick_us * t4_read_reg(padap, A_TP_RXT_MIN);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1314
tp_tick_us * t4_read_reg(padap, A_TP_RXT_MAX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1317
tp_tick_us * t4_read_reg(padap, A_TP_PERS_MIN);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1319
tp_tick_us * t4_read_reg(padap, A_TP_PERS_MAX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1322
tp_tick_us * t4_read_reg(padap, A_TP_KEEP_IDLE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1324
tp_tick_us * t4_read_reg(padap, A_TP_KEEP_INTVL);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1327
tp_tick_us * G_INITSRTT(t4_read_reg(padap, A_TP_INIT_SRTT));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1329
tp_tick_us * t4_read_reg(padap, A_TP_FINWAIT2_TIMER);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1443
tp_la_buff->mode = G_DBGLAMODE(t4_read_reg(padap, A_TP_DBG_LA_CONFIG));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1585
hw_sched_buff->map = t4_read_reg(padap, A_TP_TX_MOD_QUEUE_REQ_MAP);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1586
hw_sched_buff->mode = G_TIMERMODE(t4_read_reg(padap, A_TP_MOD_CONFIG));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1715
rss_conf->tp_rssconf = t4_read_reg(padap, A_TP_RSS_CONFIG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1716
rss_conf->tp_rssconf_tnl = t4_read_reg(padap, A_TP_RSS_CONFIG_TNL);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1717
rss_conf->tp_rssconf_ofd = t4_read_reg(padap, A_TP_RSS_CONFIG_OFD);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1718
rss_conf->tp_rssconf_syn = t4_read_reg(padap, A_TP_RSS_CONFIG_SYN);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1719
rss_conf->tp_rssconf_vrt = t4_read_reg(padap, A_TP_RSS_CONFIG_VRT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1720
rss_conf->tp_rssconf_cng = t4_read_reg(padap, A_TP_RSS_CONFIG_CNG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1885
value = t4_read_reg(padap, A_SGE_FLM_CFG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2617
value = t4_read_reg(padap, A_MA_EXT_MEMORY_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2621
value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2626
value = t4_read_reg(padap, A_MA_EXT_MEMORY0_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2630
value = t4_read_reg(padap, A_MA_EXT_MEMORY1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2634
value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2641
value = t4_read_reg(padap, A_MA_EDRAM0_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2645
value = t4_read_reg(padap, A_MA_EDRAM1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2649
value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2902
val = t4_read_reg(padap, A_CIM_HOST_ACC_CTRL);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
2927
*val = t4_read_reg(padap, A_CIM_HOST_ACC_DATA);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3288
tid->hash_base = t4_read_reg(padap, A_LE_DB_TID_HASHBASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3291
tid->hash_base = t4_read_reg(padap, A_T6_LE_DB_HASH_TID_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3292
tid1->tid_start = t4_read_reg(padap, A_LE_DB_ACTIVE_TABLE_START_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3295
tid->le_db_conf = t4_read_reg(padap, A_LE_DB_CONFIG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3360
tid->sb = t4_read_reg(padap, A_LE_DB_SERVER_INDEX) / 4;
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3363
tid->sb = t4_read_reg(padap, A_LE_DB_SRVR_START_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3379
tid->IP_users = t4_read_reg(padap, A_LE_DB_ACT_CNT_IPV4);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3380
tid->IPv6_users = t4_read_reg(padap, A_LE_DB_ACT_CNT_IPV6);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3444
mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3446
mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3448
mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3450
mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3453
mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3455
mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3457
mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3459
mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3462
mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP3));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3463
mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP2));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3464
mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP1));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3465
mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP0));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3510
val = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3512
tcamy |= t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3513
data2 = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3538
val = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3540
tcamx |= t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3541
data2 = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3557
tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(i));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3558
tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(i));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3698
val = t4_read_reg(padap, A_LE_DB_DBGI_CONFIG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3712
val = t4_read_reg(padap, A_LE_DB_DBGI_RSP_STATUS);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3723
tid_data->data[i] = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3746
value = t4_read_reg(padap, A_LE_DB_TID_HASHBASE); /* Get hash base
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3751
value = t4_read_reg(padap, A_LE_DB_ROUTING_TABLE_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3755
value = t4_read_reg(padap, A_LE_DB_CLIP_TABLE_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3759
value = t4_read_reg(padap, A_LE_DB_FILTER_TABLE_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3763
value = t4_read_reg(padap, A_LE_DB_SERVER_INDEX);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3767
value = t4_read_reg(padap, A_LE_DB_CONFIG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
3769
value = t4_read_reg(padap, A_LE_DB_HASH_CONFIG);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
4320
*sp = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_10);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
690
swstate->fw_state = t4_read_reg(padap, A_PCIE_FW);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
762
ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
765
ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
768
ulptx_la_buff->rddata[i] = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
773
t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
881
val1 = t4_read_reg(padap, A_SGE_STAT_TOTAL);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
882
val2 = t4_read_reg(padap, A_SGE_STAT_MATCH);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
933
lo = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
936
hi = t4_read_reg(padap, A_MA_EDRAM0_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
945
hi = t4_read_reg(padap, A_MA_EDRAM1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
955
hi = t4_read_reg(padap, A_MA_EXT_MEMORY0_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
965
hi = t4_read_reg(padap, A_MA_EXT_MEMORY1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
975
hi = t4_read_reg(padap, A_MA_EXT_MEMORY_BAR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
993
(md++)->base = t4_read_reg(padap, A_SGE_DBQ_CTXT_BADDR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
994
(md++)->base = t4_read_reg(padap, A_SGE_IMSG_CTXT_BADDR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
995
(md++)->base = t4_read_reg(padap, A_SGE_FLM_CACHE_BADDR);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
996
(md++)->base = t4_read_reg(padap, A_TP_CMM_TCB_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
997
(md++)->base = t4_read_reg(padap, A_TP_CMM_MM_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
998
(md++)->base = t4_read_reg(padap, A_TP_CMM_TIMER_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
999
(md++)->base = t4_read_reg(padap, A_TP_CMM_MM_RX_FLST_BASE);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1007
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1012
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1021
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1028
value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1054
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1064
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1075
value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1083
value = t4_read_reg(padap, 0x30f20 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1091
value = t4_read_reg(padap, 0x30f60 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1098
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1105
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1111
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1129
value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1138
value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1153
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1173
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1179
value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1185
value = t4_read_reg(padap, 0x30e20 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1192
value = t4_read_reg(padap, 0x30e60 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1205
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1209
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1212
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1216
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1220
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1224
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1227
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1231
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1235
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1246
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1250
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1254
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1258
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1262
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1266
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1270
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1274
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1278
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1282
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1286
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
1290
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
276
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_LOW);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
279
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
346
value = t4_read_reg(padap, A_PCIE_CMDR_REQ_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
356
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
362
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_6);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
373
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_3);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
385
value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
392
value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
401
value = t4_read_reg(padap, 0x30a80 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
407
value = t4_read_reg(padap, A_PCIE_CMDR_RSP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
452
value = t4_read_reg(padap, A_PCIE_DMAR_REQ_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
465
value = t4_read_reg(padap, A_PCIE_DMAR_RSP_SOP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
472
value = t4_read_reg(padap, A_PCIE_DMAR_RSP_EOP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
503
value = t4_read_reg(padap, (A_ULP_TX_SE_CNT_CH0 + (i*4)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
542
value = t4_read_reg(padap, 0x5988 + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
549
value = t4_read_reg(padap, 0x598c + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
556
value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
567
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
588
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
597
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
610
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
623
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
638
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
652
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
658
value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
667
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
671
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
674
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
678
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
682
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
686
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
689
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
693
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
697
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
708
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
712
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
716
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
720
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
724
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
728
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
732
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
736
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
740
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
744
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
748
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
752
value = t4_read_reg(padap,
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
760
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
840
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
849
value = t4_read_reg(padap, 0x30a88 + ((i * 4) << 12));
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
855
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
866
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
883
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
892
value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
906
value = t4_read_reg(padap, A_PCIE_DMAW_SOP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
913
value = t4_read_reg(padap, A_PCIE_DMAW_EOP_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
920
value = t4_read_reg(padap, A_PCIE_DMAI_CNT);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
979
value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT2);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
983
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
989
value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT3);
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
111
r.value = t4_read_reg(sc, r.reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
126
*p++ = t4_read_reg(sc, start);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1114
em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1119
addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1126
addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1133
addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1142
addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1455
uint32_t r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1526
val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1597
(void) t4_read_reg(sc,
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1628
(void) t4_read_reg(sc, reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2234
wc_total = t4_read_reg(sc, A_SGE_STAT_TOTAL);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2235
wc_failure = t4_read_reg(sc, A_SGE_STAT_MATCH);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2281
low = t4_read_reg(sc, T5_PORT_REG(port, lo_reg));
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2282
high = t4_read_reg(sc, T5_PORT_REG(port, high_reg));
usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
262
sge_control = t4_read_reg(sc, A_SGE_CONTROL);
usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
313
sge_conm_ctrl = t4_read_reg(sc, A_SGE_CONM_CTRL);
usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
3456
bgmap = G_NUMPORTS(t4_read_reg(pi->adapter, A_MPS_CMN_CTL));