Symbol: t1_write_reg_4
usr/src/uts/common/io/chxge/ch.c
770
t1_write_reg_4(chp->sge->obj, A_SG_CONTROL, 0x0);
usr/src/uts/common/io/chxge/ch.c
771
t1_write_reg_4(chp->sge->obj, A_SG_INT_CAUSE, 0x0);
usr/src/uts/common/io/chxge/ch.h
284
void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
usr/src/uts/common/io/chxge/com/ch_mac.c
118
t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr);
usr/src/uts/common/io/chxge/com/ch_mac.c
123
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
142
t1_write_reg_4(mac->adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/ch_mac.c
148
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
180
t1_write_reg_4(mac->adapter, MAC_REG_CSR(idx),
usr/src/uts/common/io/chxge/com/ch_mac.c
209
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
246
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
261
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
276
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
284
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
296
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
306
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
319
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
393
t1_write_reg_4(adapter, MAC_REG_CSR(mac->instance->index), data32);
usr/src/uts/common/io/chxge/com/ch_mac.c
397
t1_write_reg_4(adapter,
usr/src/uts/common/io/chxge/com/ch_mac.c
406
t1_write_reg_4(adapter, MAC_REG_IDLO(mac->instance->index),
usr/src/uts/common/io/chxge/com/ch_mac.c
408
t1_write_reg_4(adapter, MAC_REG_IDHI(mac->instance->index),
usr/src/uts/common/io/chxge/com/ch_mac.c
92
t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr);
usr/src/uts/common/io/chxge/com/ch_mac.c
97
t1_write_reg_4(mac->adapter,
usr/src/uts/common/io/chxge/com/ch_subr.c
1018
t1_write_reg_4(adapter, A_PL_ENABLE, pl_intr);
usr/src/uts/common/io/chxge/com/ch_subr.c
1051
t1_write_reg_4(adapter, A_PL_ENABLE, 0);
usr/src/uts/common/io/chxge/com/ch_subr.c
1090
t1_write_reg_4(adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/ch_subr.c
1131
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
usr/src/uts/common/io/chxge/com/ch_subr.c
119
t1_write_reg_4(adapter, A_TPI_ADDR, addr);
usr/src/uts/common/io/chxge/com/ch_subr.c
120
t1_write_reg_4(adapter, A_TPI_CSR, 0);
usr/src/uts/common/io/chxge/com/ch_subr.c
1252
t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY | F_MC4_SLOW);
usr/src/uts/common/io/chxge/com/ch_subr.c
1253
t1_write_reg_4(adapter, A_MC5_CONFIG,
usr/src/uts/common/io/chxge/com/ch_subr.c
149
t1_write_reg_4(adapter, A_TPI_PAR, V_TPIPAR(value));
usr/src/uts/common/io/chxge/com/ch_subr.c
215
t1_write_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/ch_subr.c
245
t1_write_reg_4(adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,
usr/src/uts/common/io/chxge/com/ch_subr.c
257
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
usr/src/uts/common/io/chxge/com/ch_subr.c
268
t1_write_reg_4(adapter, A_MI0_CLK, V_MI0_CLK_DIV(3));
usr/src/uts/common/io/chxge/com/ch_subr.c
286
t1_write_reg_4(adapter, A_MI0_ADDR,
usr/src/uts/common/io/chxge/com/ch_subr.c
305
t1_write_reg_4(adapter, A_MI0_ADDR,
usr/src/uts/common/io/chxge/com/ch_subr.c
307
t1_write_reg_4(adapter, A_MI0_DATA_EXT, val);
usr/src/uts/common/io/chxge/com/ch_subr.c
88
t1_write_reg_4(adapter, A_TPI_ADDR, addr);
usr/src/uts/common/io/chxge/com/ch_subr.c
89
t1_write_reg_4(adapter, A_TPI_WR_DATA, value);
usr/src/uts/common/io/chxge/com/ch_subr.c
90
t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR);
usr/src/uts/common/io/chxge/com/cspi.c
36
t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0xffffffff);
usr/src/uts/common/io/chxge/com/cspi.c
42
t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0);
usr/src/uts/common/io/chxge/com/cspi.c
60
t1_write_reg_4(adapter, A_CSPI_CALENDAR_LEN, 15);
usr/src/uts/common/io/chxge/com/cspi.c
61
t1_write_reg_4(adapter, A_CSPI_FIFO_STATUS_ENABLE, 1);
usr/src/uts/common/io/chxge/com/espi.c
104
t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST);
usr/src/uts/common/io/chxge/com/espi.c
120
t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST);
usr/src/uts/common/io/chxge/com/espi.c
137
t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
usr/src/uts/common/io/chxge/com/espi.c
138
t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
usr/src/uts/common/io/chxge/com/espi.c
144
t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
usr/src/uts/common/io/chxge/com/espi.c
145
t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
usr/src/uts/common/io/chxge/com/espi.c
152
t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0);
usr/src/uts/common/io/chxge/com/espi.c
153
t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI);
usr/src/uts/common/io/chxge/com/espi.c
181
t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
usr/src/uts/common/io/chxge/com/espi.c
194
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
195
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
196
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
197
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
198
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
usr/src/uts/common/io/chxge/com/espi.c
199
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
usr/src/uts/common/io/chxge/com/espi.c
200
t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
usr/src/uts/common/io/chxge/com/espi.c
201
t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
usr/src/uts/common/io/chxge/com/espi.c
202
t1_write_reg_4(adapter, A_PORT_CONFIG,
usr/src/uts/common/io/chxge/com/espi.c
211
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
212
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
213
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
214
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
215
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
usr/src/uts/common/io/chxge/com/espi.c
216
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
usr/src/uts/common/io/chxge/com/espi.c
217
t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
usr/src/uts/common/io/chxge/com/espi.c
218
t1_write_reg_4(adapter, A_PORT_CONFIG,
usr/src/uts/common/io/chxge/com/espi.c
221
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
222
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f401f4);
usr/src/uts/common/io/chxge/com/espi.c
223
t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
usr/src/uts/common/io/chxge/com/espi.c
224
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, 0xa00);
usr/src/uts/common/io/chxge/com/espi.c
225
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x1ff);
usr/src/uts/common/io/chxge/com/espi.c
226
t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
usr/src/uts/common/io/chxge/com/espi.c
227
t1_write_reg_4(adapter, A_PORT_CONFIG,
usr/src/uts/common/io/chxge/com/espi.c
230
t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
usr/src/uts/common/io/chxge/com/espi.c
238
t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
usr/src/uts/common/io/chxge/com/espi.c
241
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
243
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
246
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
248
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
252
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
254
t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
usr/src/uts/common/io/chxge/com/espi.c
257
t1_write_reg_4(adapter, A_PORT_CONFIG,
usr/src/uts/common/io/chxge/com/espi.c
267
t1_write_reg_4(adapter, A_ESPI_TRAIN, 0);
usr/src/uts/common/io/chxge/com/espi.c
270
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
usr/src/uts/common/io/chxge/com/espi.c
273
t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2,
usr/src/uts/common/io/chxge/com/espi.c
276
t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, 0x800100);
usr/src/uts/common/io/chxge/com/espi.c
288
t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE,
usr/src/uts/common/io/chxge/com/espi.c
302
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
usr/src/uts/common/io/chxge/com/espi.c
335
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
usr/src/uts/common/io/chxge/com/espi.c
353
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
usr/src/uts/common/io/chxge/com/espi.c
356
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
usr/src/uts/common/io/chxge/com/espi.c
384
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
usr/src/uts/common/io/chxge/com/espi.c
388
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
usr/src/uts/common/io/chxge/com/espi.c
394
t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
usr/src/uts/common/io/chxge/com/espi.c
52
t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
usr/src/uts/common/io/chxge/com/espi.c
57
t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
usr/src/uts/common/io/chxge/com/espi.c
75
t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
usr/src/uts/common/io/chxge/com/espi.c
80
t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
usr/src/uts/common/io/chxge/com/mc3.c
101
t1_write_reg_4(mc3->adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/mc3.c
164
t1_write_reg_4(adapter, A_MC3_INT_ENABLE, cause);
usr/src/uts/common/io/chxge/com/mc3.c
166
t1_write_reg_4(adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
usr/src/uts/common/io/chxge/com/mc3.c
168
t1_write_reg_4(adapter, cause_reg, cause);
usr/src/uts/common/io/chxge/com/mc3.c
182
t1_write_reg_4(adapter, addr, val);
usr/src/uts/common/io/chxge/com/mc3.c
225
t1_write_reg_4(adapter, A_MC3_CFG, val);
usr/src/uts/common/io/chxge/com/mc3.c
228
t1_write_reg_4(adapter, A_MC3_CFG, val | F_CLK_ENABLE);
usr/src/uts/common/io/chxge/com/mc3.c
234
t1_write_reg_4(adapter, A_MC3_STROBE,
usr/src/uts/common/io/chxge/com/mc3.c
241
t1_write_reg_4(adapter, A_MC3_STROBE,
usr/src/uts/common/io/chxge/com/mc3.c
293
t1_write_reg_4(adapter, A_MC3_REFRESH,
usr/src/uts/common/io/chxge/com/mc3.c
297
t1_write_reg_4(adapter, A_MC3_ECC_CNTL,
usr/src/uts/common/io/chxge/com/mc3.c
301
t1_write_reg_4(adapter, A_MC3_BIST_ADDR_BEG, 0);
usr/src/uts/common/io/chxge/com/mc3.c
302
t1_write_reg_4(adapter, A_MC3_BIST_ADDR_END, (mc3->size << width) - 1);
usr/src/uts/common/io/chxge/com/mc3.c
303
t1_write_reg_4(adapter, A_MC3_BIST_DATA, 0);
usr/src/uts/common/io/chxge/com/mc3.c
304
t1_write_reg_4(adapter, A_MC3_BIST_OP, V_OP(1) | 0x1f0);
usr/src/uts/common/io/chxge/com/mc3.c
319
t1_write_reg_4(adapter, A_MC3_CFG, val | F_READY);
usr/src/uts/common/io/chxge/com/mc3.c
49
t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
usr/src/uts/common/io/chxge/com/mc3.c
50
t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3);
usr/src/uts/common/io/chxge/com/mc3.c
53
t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE,
usr/src/uts/common/io/chxge/com/mc3.c
55
t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc3.c
66
t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/mc3.c
67
t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc3.c
71
t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, 0);
usr/src/uts/common/io/chxge/com/mc3.c
72
t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc3.c
89
t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE,
usr/src/uts/common/io/chxge/com/mc3.c
91
t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, old_en);
usr/src/uts/common/io/chxge/com/mc3.c
93
t1_write_reg_4(mc3->adapter, A_MC3_INT_CAUSE,
usr/src/uts/common/io/chxge/com/mc3.c
96
t1_write_reg_4(mc3->adapter, A_PL_CAUSE, F_PL_INTR_MC3);
usr/src/uts/common/io/chxge/com/mc3.c
99
t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRCAUSE,
usr/src/uts/common/io/chxge/com/mc4.c
101
t1_write_reg_4(adapter, A_MC4_STROBE,
usr/src/uts/common/io/chxge/com/mc4.c
114
t1_write_reg_4(adapter, A_MC4_STROBE,
usr/src/uts/common/io/chxge/com/mc4.c
157
t1_write_reg_4(adapter, A_MC4_REFRESH,
usr/src/uts/common/io/chxge/com/mc4.c
161
t1_write_reg_4(adapter, A_MC4_ECC_CNTL,
usr/src/uts/common/io/chxge/com/mc4.c
165
t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0);
usr/src/uts/common/io/chxge/com/mc4.c
166
t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1);
usr/src/uts/common/io/chxge/com/mc4.c
167
t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0);
usr/src/uts/common/io/chxge/com/mc4.c
168
t1_write_reg_4(adapter, A_MC4_BIST_OP, V_OP(1) | 0x1f0);
usr/src/uts/common/io/chxge/com/mc4.c
183
t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY);
usr/src/uts/common/io/chxge/com/mc4.c
215
t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, MC4_INT_MASK);
usr/src/uts/common/io/chxge/com/mc4.c
218
t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc4.c
228
t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/mc4.c
231
t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc4.c
239
t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/com/mc4.c
240
t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4);
usr/src/uts/common/io/chxge/com/mc4.c
283
t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/mc4.c
309
t1_write_reg_4(adap, A_MC4_BD_ADDR, start);
usr/src/uts/common/io/chxge/com/mc4.c
310
t1_write_reg_4(adap, A_MC4_BD_OP, 0);
usr/src/uts/common/io/chxge/com/mc4.c
66
t1_write_reg_4(adapter, addr, val);
usr/src/uts/common/io/chxge/com/mc4.c
90
t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP);
usr/src/uts/common/io/chxge/com/mc5.c
127
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_CMD, cmd);
usr/src/uts/common/io/chxge/com/mc5.c
141
t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base);
usr/src/uts/common/io/chxge/com/mc5.c
161
t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base);
usr/src/uts/common/io/chxge/com/mc5.c
180
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, v1);
usr/src/uts/common/io/chxge/com/mc5.c
181
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR1, v2);
usr/src/uts/common/io/chxge/com/mc5.c
182
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR2, v3);
usr/src/uts/common/io/chxge/com/mc5.c
187
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA0, v1);
usr/src/uts/common/io/chxge/com/mc5.c
188
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA1, v2);
usr/src/uts/common/io/chxge/com/mc5.c
189
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA2, v3);
usr/src/uts/common/io/chxge/com/mc5.c
206
t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, addr_lo);
usr/src/uts/common/io/chxge/com/mc5.c
239
t1_write_reg_4(adap, A_MC5_DBGI_REQ_DATA0,
usr/src/uts/common/io/chxge/com/mc5.c
253
t1_write_reg_4(adap, A_MC5_RSP_LATENCY,
usr/src/uts/common/io/chxge/com/mc5.c
257
t1_write_reg_4(adap, A_MC5_AOPEN_SRCH_CMD, 0x20022);
usr/src/uts/common/io/chxge/com/mc5.c
258
t1_write_reg_4(adap, A_MC5_SYN_SRCH_CMD, 0x20022);
usr/src/uts/common/io/chxge/com/mc5.c
259
t1_write_reg_4(adap, A_MC5_ACK_SRCH_CMD, 0x20022);
usr/src/uts/common/io/chxge/com/mc5.c
263
t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_LARA_7000);
usr/src/uts/common/io/chxge/com/mc5.c
318
t1_write_reg_4(adap, A_MC5_RSP_LATENCY, 0x151515);
usr/src/uts/common/io/chxge/com/mc5.c
319
t1_write_reg_4(adap, A_MC5_PART_ID_INDEX, 2);
usr/src/uts/common/io/chxge/com/mc5.c
325
t1_write_reg_4(adap, A_MC5_POPEN_DATA_WR_CMD, MC5_IDT_CMD_WRITE);
usr/src/uts/common/io/chxge/com/mc5.c
326
t1_write_reg_4(adap, A_MC5_POPEN_MASK_WR_CMD, MC5_IDT_CMD_WRITE);
usr/src/uts/common/io/chxge/com/mc5.c
327
t1_write_reg_4(adap, A_MC5_AOPEN_SRCH_CMD, MC5_IDT_CMD_SEARCH);
usr/src/uts/common/io/chxge/com/mc5.c
328
t1_write_reg_4(adap, A_MC5_AOPEN_LRN_CMD, MC5_IDT_CMD_LEARN);
usr/src/uts/common/io/chxge/com/mc5.c
329
t1_write_reg_4(adap, A_MC5_SYN_SRCH_CMD, MC5_IDT_CMD_SEARCH | 0x6000);
usr/src/uts/common/io/chxge/com/mc5.c
330
t1_write_reg_4(adap, A_MC5_SYN_LRN_CMD, MC5_IDT_CMD_LEARN);
usr/src/uts/common/io/chxge/com/mc5.c
331
t1_write_reg_4(adap, A_MC5_ACK_SRCH_CMD, MC5_IDT_CMD_SEARCH);
usr/src/uts/common/io/chxge/com/mc5.c
332
t1_write_reg_4(adap, A_MC5_ACK_LRN_CMD, MC5_IDT_CMD_LEARN);
usr/src/uts/common/io/chxge/com/mc5.c
333
t1_write_reg_4(adap, A_MC5_ILOOKUP_CMD, MC5_IDT_CMD_SEARCH);
usr/src/uts/common/io/chxge/com/mc5.c
334
t1_write_reg_4(adap, A_MC5_ELOOKUP_CMD, MC5_IDT_CMD_SEARCH | 0x7000);
usr/src/uts/common/io/chxge/com/mc5.c
335
t1_write_reg_4(adap, A_MC5_DATA_WRITE_CMD, MC5_IDT_CMD_WRITE);
usr/src/uts/common/io/chxge/com/mc5.c
336
t1_write_reg_4(adap, A_MC5_DATA_READ_CMD, MC5_IDT_CMD_READ);
usr/src/uts/common/io/chxge/com/mc5.c
339
t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_IDT_52100);
usr/src/uts/common/io/chxge/com/mc5.c
381
t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
usr/src/uts/common/io/chxge/com/mc5.c
389
t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
usr/src/uts/common/io/chxge/com/mc5.c
412
t1_write_reg_4(adap, A_MC5_CONFIG, cfg);
usr/src/uts/common/io/chxge/com/mc5.c
430
t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR1, 0);
usr/src/uts/common/io/chxge/com/mc5.c
431
t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR2, 0);
usr/src/uts/common/io/chxge/com/mc5.c
478
t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR0, start++);
usr/src/uts/common/io/chxge/com/mc5.c
514
t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, mask);
usr/src/uts/common/io/chxge/com/mc5.c
520
t1_write_reg_4(mc5->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc5.c
522
t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE,
usr/src/uts/common/io/chxge/com/mc5.c
532
t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/mc5.c
538
t1_write_reg_4(mc5->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/mc5.c
540
t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/mc5.c
548
t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/com/mc5.c
552
t1_write_reg_4(mc5->adapter, A_PL_CAUSE, F_PL_INTR_MC5);
usr/src/uts/common/io/chxge/com/mc5.c
553
t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/com/mc5.c
624
t1_write_reg_4(adap, A_MC5_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/mc5.c
695
t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
usr/src/uts/common/io/chxge/com/mc5.c
700
t1_write_reg_4(mc5->adapter, A_MC5_LIP_RAM_DATA, p[i]);
usr/src/uts/common/io/chxge/com/mc5.c
701
t1_write_reg_4(mc5->adapter, A_MC5_LIP_RAM_ADDR, 0x100 + i);
usr/src/uts/common/io/chxge/com/mc5.c
705
t1_write_reg_4(mc5->adapter, A_MC5_CONFIG, cfg | F_COMPRESSION_ENABLE);
usr/src/uts/common/io/chxge/com/pm3393.c
167
t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr);
usr/src/uts/common/io/chxge/com/pm3393.c
249
t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr);
usr/src/uts/common/io/chxge/com/tp.c
109
t1_write_reg_4(adapter, A_TP_2MSL, (1 SECONDS)/2);
usr/src/uts/common/io/chxge/com/tp.c
110
t1_write_reg_4(adapter, A_TP_RXT_MIN, (1 SECONDS)/4);
usr/src/uts/common/io/chxge/com/tp.c
111
t1_write_reg_4(adapter, A_TP_RXT_MAX, 64 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
112
t1_write_reg_4(adapter, A_TP_PERS_MIN, (1 SECONDS)/2);
usr/src/uts/common/io/chxge/com/tp.c
113
t1_write_reg_4(adapter, A_TP_PERS_MAX, 64 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
114
t1_write_reg_4(adapter, A_TP_KEEP_IDLE, 7200 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
115
t1_write_reg_4(adapter, A_TP_KEEP_INTVL, 75 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
116
t1_write_reg_4(adapter, A_TP_INIT_SRTT, 3 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
117
t1_write_reg_4(adapter, A_TP_FINWAIT2_TIME, 60 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
118
t1_write_reg_4(adapter, A_TP_FAST_FINWAIT2_TIME, 3 SECONDS);
usr/src/uts/common/io/chxge/com/tp.c
125
t1_write_reg_4(adapter, A_TP_SHIFT_CNT, tp_scnt);
usr/src/uts/common/io/chxge/com/tp.c
128
t1_write_reg_4(adapter, A_TP_DACK_TIME,
usr/src/uts/common/io/chxge/com/tp.c
148
t1_write_reg_4(tp->adapter, A_TP_PARA_REG2,
usr/src/uts/common/io/chxge/com/tp.c
155
t1_write_reg_4(tp->adapter, A_TP_PARA_REG3, val);
usr/src/uts/common/io/chxge/com/tp.c
164
t1_write_reg_4(adap, A_TP_MIB_INDEX, 0);
usr/src/uts/common/io/chxge/com/tp.c
184
t1_write_reg_4(ap, A_TP_IN_CONFIG, val);
usr/src/uts/common/io/chxge/com/tp.c
185
t1_write_reg_4(ap, A_TP_OUT_CONFIG, F_TP_OUT_CSPI_CPL |
usr/src/uts/common/io/chxge/com/tp.c
189
t1_write_reg_4(ap, A_TP_GLOBAL_CONFIG, V_IP_TTL(64) |
usr/src/uts/common/io/chxge/com/tp.c
200
t1_write_reg_4(ap, A_TP_TX_DROP_CONFIG,
usr/src/uts/common/io/chxge/com/tp.c
207
t1_write_reg_4(ap, A_TP_GLOBAL_RX_CREDITS, 0xffffffff);
usr/src/uts/common/io/chxge/com/tp.c
215
t1_write_reg_4(ap, A_TP_TCP_OPTIONS, val);
usr/src/uts/common/io/chxge/com/tp.c
216
t1_write_reg_4(ap, A_TP_DACK_CONFIG, V_DACK_MSS_SELECTOR(1) |
usr/src/uts/common/io/chxge/com/tp.c
218
t1_write_reg_4(ap, A_TP_BACKOFF0, 0x3020100);
usr/src/uts/common/io/chxge/com/tp.c
219
t1_write_reg_4(ap, A_TP_BACKOFF1, 0x7060504);
usr/src/uts/common/io/chxge/com/tp.c
220
t1_write_reg_4(ap, A_TP_BACKOFF2, 0xb0a0908);
usr/src/uts/common/io/chxge/com/tp.c
221
t1_write_reg_4(ap, A_TP_BACKOFF3, 0xf0e0d0c);
usr/src/uts/common/io/chxge/com/tp.c
228
t1_write_reg_4(ap, A_TP_PARA_REG0, 0xd1269324);
usr/src/uts/common/io/chxge/com/tp.c
230
t1_write_reg_4(ap, A_TP_PARA_REG0, 0xd6269324);
usr/src/uts/common/io/chxge/com/tp.c
231
t1_write_reg_4(ap, A_TP_SYNC_TIME_HI, 0);
usr/src/uts/common/io/chxge/com/tp.c
232
t1_write_reg_4(ap, A_TP_SYNC_TIME_LO, 0);
usr/src/uts/common/io/chxge/com/tp.c
233
t1_write_reg_4(ap, A_TP_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/tp.c
234
t1_write_reg_4(ap, A_TP_CM_FC_MODE, 0); /* Enable CM cache */
usr/src/uts/common/io/chxge/com/tp.c
235
t1_write_reg_4(ap, A_TP_PC_CONGESTION_CNTL, 0x6186);
usr/src/uts/common/io/chxge/com/tp.c
259
t1_write_reg_4(ap, A_TP_TIMER_SEPARATOR, val & ~1);
usr/src/uts/common/io/chxge/com/tp.c
261
t1_write_reg_4(ap, A_TP_TIMER_RESOLUTION, 0xF0011);
usr/src/uts/common/io/chxge/com/tp.c
268
t1_write_reg_4(ap, A_TP_PC_CONFIG, val);
usr/src/uts/common/io/chxge/com/tp.c
273
t1_write_reg_4(ap, A_TP_TIMER_RESOLUTION, 0xD000A);
usr/src/uts/common/io/chxge/com/tp.c
322
t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE,
usr/src/uts/common/io/chxge/com/tp.c
324
t1_write_reg_4(tp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/tp.c
330
t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/tp.c
331
t1_write_reg_4(tp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/tp.c
343
t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/tp.c
344
t1_write_reg_4(tp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/tp.c
349
t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/tp.c
350
t1_write_reg_4(tp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/tp.c
359
t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,
usr/src/uts/common/io/chxge/com/tp.c
361
t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP);
usr/src/uts/common/io/chxge/com/tp.c
365
t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/com/tp.c
366
t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP);
usr/src/uts/common/io/chxge/com/tp.c
380
t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/tp.c
392
t1_write_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG, val);
usr/src/uts/common/io/chxge/com/tp.c
425
t1_write_reg_4(adapter, A_TP_RESET, F_CM_MEMMGR_INIT);
usr/src/uts/common/io/chxge/com/tp.c
431
t1_write_reg_4(adapter, A_TP_RESET, F_TP_RESET);
usr/src/uts/common/io/chxge/com/tp.c
62
t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size);
usr/src/uts/common/io/chxge/com/tp.c
63
t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base);
usr/src/uts/common/io/chxge/com/tp.c
64
t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base);
usr/src/uts/common/io/chxge/com/tp.c
65
t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size);
usr/src/uts/common/io/chxge/com/tp.c
66
t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size);
usr/src/uts/common/io/chxge/com/tp.c
67
t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs);
usr/src/uts/common/io/chxge/com/tp.c
68
t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size);
usr/src/uts/common/io/chxge/com/tp.c
69
t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs);
usr/src/uts/common/io/chxge/com/tp.c
77
t1_write_reg_4(adapter, A_TP_CM_SIZE, cm_size);
usr/src/uts/common/io/chxge/com/tp.c
78
t1_write_reg_4(adapter, A_TP_CM_MM_BASE, mm_base);
usr/src/uts/common/io/chxge/com/tp.c
79
t1_write_reg_4(adapter, A_TP_CM_TIMER_BASE, (cm_size >> 2) * 3);
usr/src/uts/common/io/chxge/com/tp.c
80
t1_write_reg_4(adapter, A_TP_CM_MM_P_FLST_BASE,
usr/src/uts/common/io/chxge/com/tp.c
82
t1_write_reg_4(adapter, A_TP_CM_MM_TX_FLST_BASE,
usr/src/uts/common/io/chxge/com/tp.c
84
t1_write_reg_4(adapter, A_TP_CM_MM_RX_FLST_BASE,
usr/src/uts/common/io/chxge/com/tp.c
86
t1_write_reg_4(adapter, A_TP_CM_MM_MAX_P, 0x40000);
usr/src/uts/common/io/chxge/com/ulp.c
113
t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/ulp.c
133
t1_write_reg_4(adapter, A_ULP_HREG_INDEX, i);
usr/src/uts/common/io/chxge/com/ulp.c
134
t1_write_reg_4(adapter, A_ULP_HREG_DATA, 0);
usr/src/uts/common/io/chxge/com/ulp.c
137
t1_write_reg_4(adapter, A_ULP_ULIMIT, pm_tx_base);
usr/src/uts/common/io/chxge/com/ulp.c
138
t1_write_reg_4(adapter, A_ULP_TAGMASK, (pm_tx_base << 1) - 1);
usr/src/uts/common/io/chxge/com/ulp.c
142
t1_write_reg_4(adapter, A_ULP_HREG_INDEX, 0);
usr/src/uts/common/io/chxge/com/ulp.c
144
t1_write_reg_4(adapter, A_ULP_PIO_CTRL, 1);
usr/src/uts/common/io/chxge/com/ulp.c
47
t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, ULP_INTR_MASK);
usr/src/uts/common/io/chxge/com/ulp.c
48
t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/ulp.c
56
t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP);
usr/src/uts/common/io/chxge/com/ulp.c
57
t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/com/ulp.c
66
t1_write_reg_4(ulp->adapter, A_PL_ENABLE,
usr/src/uts/common/io/chxge/com/ulp.c
68
t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/glue.c
244
t1_write_reg_4(chp, pe->addr, pe->pe_reg_val);
usr/src/uts/common/io/chxge/pe.c
1519
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT);
usr/src/uts/common/io/chxge/pe.c
1521
t1_write_reg_4(adapter, A_PL_ENABLE, enable | F_PL_INTR_EXT);
usr/src/uts/common/io/chxge/pe.c
1534
t1_write_reg_4(adapter, A_PL_ENABLE, enable & ~F_PL_INTR_EXT);
usr/src/uts/common/io/chxge/pe.c
1598
t1_write_reg_4(adapter, MTUREG(i), mtu);
usr/src/uts/common/io/chxge/sge.c
1151
t1_write_reg_4(sge->obj, A_SG_INTRTIMER, irqholdoff_reg);
usr/src/uts/common/io/chxge/sge.c
1152
t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, irq_reg);
usr/src/uts/common/io/chxge/sge.c
123
t1_write_reg_4(sge->obj, A_SG_DOORBELL, control_reg);
usr/src/uts/common/io/chxge/sge.c
1422
t1_write_reg_4(sge->obj, A_SG_INTRTIMER, newTimer);
usr/src/uts/common/io/chxge/sge.c
1437
t1_write_reg_4(ap, A_SG_CONTROL, 0);
usr/src/uts/common/io/chxge/sge.c
1451
t1_write_reg_4(ap, A_SG_FLTHRESHOLD, SGE_RX_SM_BUF_SIZE(ap) -
usr/src/uts/common/io/chxge/sge.c
1455
t1_write_reg_4(ap, A_SG_RSPQUEUECREDIT, (u32)sge->respQ.rq_entries_n);
usr/src/uts/common/io/chxge/sge.c
1496
t1_write_reg_4(ap, A_SG_INTRTIMER,
usr/src/uts/common/io/chxge/sge.c
1506
t1_write_reg_4(adapter, base_reg_lo, (u32)addr);
usr/src/uts/common/io/chxge/sge.c
1507
t1_write_reg_4(adapter, base_reg_hi, addr >> 32);
usr/src/uts/common/io/chxge/sge.c
1508
t1_write_reg_4(adapter, size_reg, size);
usr/src/uts/common/io/chxge/sge.c
263
t1_write_reg_4(sge->obj, A_SG_CONTROL, sge->sge_control);
usr/src/uts/common/io/chxge/sge.c
283
t1_write_reg_4(sge->obj, A_SG_CONTROL, 0x0);
usr/src/uts/common/io/chxge/sge.c
289
t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, status);
usr/src/uts/common/io/chxge/sge.c
508
t1_write_reg_4(sge->obj, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK);
usr/src/uts/common/io/chxge/sge.c
509
t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, 0);
usr/src/uts/common/io/chxge/sge.c
525
t1_write_reg_4(sge->obj, A_PL_ENABLE, val | SGE_PL_INTR_MASK);
usr/src/uts/common/io/chxge/sge.c
529
t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, en);
usr/src/uts/common/io/chxge/sge.c
539
t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK);
usr/src/uts/common/io/chxge/sge.c
540
t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, 0xffffffff);
usr/src/uts/common/io/chxge/sge.c
576
t1_write_reg_4(obj, A_SG_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/sge.c
604
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_SGE_DATA);
usr/src/uts/common/io/chxge/sge.c
624
t1_write_reg_4(adapter, A_SG_RSPQUEUECREDIT, n);
usr/src/uts/common/io/chxge/sge.c
737
t1_write_reg_4(adapter, A_SG_SLEEPING, cidx);