Symbol: t1_tpi_write
usr/src/uts/common/io/chxge/com/ch_subr.c
1159
(void) t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
usr/src/uts/common/io/chxge/com/ch_subr.c
1198
(void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
usr/src/uts/common/io/chxge/com/ch_subr.c
1202
(void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
usr/src/uts/common/io/chxge/com/ch_subr.c
1214
(void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
usr/src/uts/common/io/chxge/com/ch_subr.c
1219
(void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
usr/src/uts/common/io/chxge/com/ch_subr.c
350
(void) t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
usr/src/uts/common/io/chxge/com/ch_subr.c
966
(void) t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
usr/src/uts/common/io/chxge/com/common.h
238
int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
usr/src/uts/common/io/chxge/com/ixf1010.c
169
(void) t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val);
usr/src/uts/common/io/chxge/com/ixf1010.c
236
(void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo);
usr/src/uts/common/io/chxge/com/ixf1010.c
237
(void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi);
usr/src/uts/common/io/chxge/com/ixf1010.c
279
(void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode);
usr/src/uts/common/io/chxge/com/ixf1010.c
282
(void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0);
usr/src/uts/common/io/chxge/com/ixf1010.c
283
(void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0);
usr/src/uts/common/io/chxge/com/ixf1010.c
290
(void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo);
usr/src/uts/common/io/chxge/com/ixf1010.c
291
(void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi);
usr/src/uts/common/io/chxge/com/ixf1010.c
303
(void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE),
usr/src/uts/common/io/chxge/com/ixf1010.c
320
(void) t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val);
usr/src/uts/common/io/chxge/com/ixf1010.c
329
(void) t1_tpi_write(mac->adapter, MACREG(mac, REG_FC_ENABLE), val);
usr/src/uts/common/io/chxge/com/ixf1010.c
364
(void) t1_tpi_write(adapter, MACREG(mac, REG_DIVERSE_CONFIG), val);
usr/src/uts/common/io/chxge/com/ixf1010.c
366
(void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 3);
usr/src/uts/common/io/chxge/com/ixf1010.c
368
(void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 2);
usr/src/uts/common/io/chxge/com/ixf1010.c
372
(void) t1_tpi_write(adapter, REG_RX_ERR_DROP, val);
usr/src/uts/common/io/chxge/com/ixf1010.c
384
(void) t1_tpi_write(adapter, REG_PORT_ENABLE, val);
usr/src/uts/common/io/chxge/com/ixf1010.c
390
(void) t1_tpi_write(adapter, RX_FIFO_HIGH_WATERMARK_BASE + index, 0x740);
usr/src/uts/common/io/chxge/com/ixf1010.c
391
(void) t1_tpi_write(adapter, RX_FIFO_LOW_WATERMARK_BASE + index, 0x730);
usr/src/uts/common/io/chxge/com/ixf1010.c
392
(void) t1_tpi_write(adapter, TX_FIFO_HIGH_WATERMARK_BASE + index, 0x600);
usr/src/uts/common/io/chxge/com/ixf1010.c
393
(void) t1_tpi_write(adapter, TX_FIFO_LOW_WATERMARK_BASE + index, 0x1d0);
usr/src/uts/common/io/chxge/com/ixf1010.c
394
(void) t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x1100);
usr/src/uts/common/io/chxge/com/ixf1010.c
400
(void) t1_tpi_write(adapter,
usr/src/uts/common/io/chxge/com/ixf1010.c
497
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/ixf1010.c
501
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/ixf1010.c
504
(void) t1_tpi_write(adapter, REG_PORT_ENABLE, 0);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
104
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
123
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
142
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
usr/src/uts/common/io/chxge/com/mv88x201x.c
100
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/mv88x201x.c
137
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
usr/src/uts/common/io/chxge/com/mv88x201x.c
247
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/mv88x201x.c
250
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
usr/src/uts/common/io/chxge/com/mv88x201x.c
256
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/mv88x201x.c
84
(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/my3126.c
110
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/my3126.c
114
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/my3126.c
154
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/my3126.c
229
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/my3126.c
232
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
usr/src/uts/common/io/chxge/com/my3126.c
238
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/my3126.c
99
(void) t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
usr/src/uts/common/io/chxge/com/pm3393.c
101
(void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
usr/src/uts/common/io/chxge/com/pm3393.c
161
(void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/pm3393.c
200
(void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
usr/src/uts/common/io/chxge/com/pm3393.c
243
(void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
usr/src/uts/common/io/chxge/com/pm3393.c
742
(void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
usr/src/uts/common/io/chxge/com/pm3393.c
743
(void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
usr/src/uts/common/io/chxge/com/pm3393.c
744
(void) t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
usr/src/uts/common/io/chxge/com/pm3393.c
745
(void) t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
usr/src/uts/common/io/chxge/com/pm3393.c
746
(void) t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
747
(void) t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
748
(void) t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
749
(void) t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
750
(void) t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
751
(void) t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
752
(void) t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
753
(void) t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
754
(void) t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
755
(void) t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
756
(void) t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
757
(void) t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
758
(void) t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
759
(void) t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
760
(void) t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
761
(void) t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
usr/src/uts/common/io/chxge/com/pm3393.c
762
(void) t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
usr/src/uts/common/io/chxge/com/pm3393.c
763
(void) t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
usr/src/uts/common/io/chxge/com/pm3393.c
765
(void) t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
usr/src/uts/common/io/chxge/com/pm3393.c
766
(void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
usr/src/uts/common/io/chxge/com/pm3393.c
767
(void) t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
768
(void) t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
769
(void) t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
usr/src/uts/common/io/chxge/com/pm3393.c
770
(void) t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
usr/src/uts/common/io/chxge/com/pm3393.c
771
(void) t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
usr/src/uts/common/io/chxge/com/pm3393.c
772
(void) t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
usr/src/uts/common/io/chxge/com/pm3393.c
773
(void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
usr/src/uts/common/io/chxge/com/pm3393.c
774
(void) t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
775
(void) t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
776
(void) t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
777
(void) t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
779
(void) t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
usr/src/uts/common/io/chxge/com/pm3393.c
780
(void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
usr/src/uts/common/io/chxge/com/pm3393.c
781
(void) t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
782
(void) t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
783
(void) t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
784
(void) t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
usr/src/uts/common/io/chxge/com/pm3393.c
785
(void) t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
usr/src/uts/common/io/chxge/com/pm3393.c
786
(void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
usr/src/uts/common/io/chxge/com/pm3393.c
787
(void) t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
788
(void) t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
789
(void) t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
791
(void) t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
792
(void) t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
usr/src/uts/common/io/chxge/com/pm3393.c
793
(void) t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
usr/src/uts/common/io/chxge/com/pm3393.c
794
(void) t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
usr/src/uts/common/io/chxge/com/pm3393.c
795
(void) t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
usr/src/uts/common/io/chxge/com/pm3393.c
796
(void) t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
usr/src/uts/common/io/chxge/com/pm3393.c
798
(void) t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
usr/src/uts/common/io/chxge/com/pm3393.c
799
(void) t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
usr/src/uts/common/io/chxge/com/pm3393.c
801
(void) t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
usr/src/uts/common/io/chxge/com/pm3393.c
802
(void) t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
usr/src/uts/common/io/chxge/com/pm3393.c
804
(void) t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
usr/src/uts/common/io/chxge/com/pm3393.c
806
(void) t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
usr/src/uts/common/io/chxge/com/pm3393.c
807
(void) t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
usr/src/uts/common/io/chxge/com/pm3393.c
808
(void) t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
usr/src/uts/common/io/chxge/com/pm3393.c
809
(void) t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
usr/src/uts/common/io/chxge/com/pm3393.c
813
(void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
usr/src/uts/common/io/chxge/com/pm3393.c
814
(void) t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
usr/src/uts/common/io/chxge/com/pm3393.c
815
(void) t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
usr/src/uts/common/io/chxge/com/pm3393.c
816
(void) t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
usr/src/uts/common/io/chxge/com/pm3393.c
817
(void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
usr/src/uts/common/io/chxge/com/pm3393.c
819
(void) t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
usr/src/uts/common/io/chxge/com/pm3393.c
820
(void) t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
usr/src/uts/common/io/chxge/com/pm3393.c
821
(void) t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
usr/src/uts/common/io/chxge/com/pm3393.c
870
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/pm3393.c
883
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/vsc7321.c
104
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/vsc7321.c
84
(void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
usr/src/uts/common/io/chxge/com/vsc7321.c
85
(void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
usr/src/uts/common/io/chxge/com/vsc7321.c
95
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/vsc7326.c
100
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/vsc7326.c
104
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/vsc7326.c
84
(void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
usr/src/uts/common/io/chxge/com/vsc7326.c
85
(void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
usr/src/uts/common/io/chxge/com/xpak.c
129
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/com/xpak.c
136
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
usr/src/uts/common/io/chxge/com/xpak.c
144
(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
usr/src/uts/common/io/chxge/glue.c
335
(void) t1_tpi_write(chp, te->addr, te->val);
usr/src/uts/common/io/chxge/sge.c
1032
(void) t1_tpi_write(adapter,
usr/src/uts/common/io/chxge/sge.c
1044
(void) t1_tpi_write(adapter,