usr/src/uts/common/io/chxge/ch.h

283

uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);

usr/src/uts/common/io/chxge/com/ch_mac.c

116

mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/ch_mac.c

120

mac_intr = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

145

mac_intr = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

159

data32_lo = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

161

data32_hi = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

179

data32 = t1_read_reg_4(mac->adapter, MAC_REG_CSR(idx));

usr/src/uts/common/io/chxge/com/ch_mac.c

184

data32 = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

204

val = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

220

data32 = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

255

val = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

270

val = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

293

u32 data32 = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

322

*p++ = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_mac.c

389

data32 = t1_read_reg_4(adapter, MAC_REG_CSR(mac->instance->index));

usr/src/uts/common/io/chxge/com/ch_mac.c

401

data32 = t1_read_reg_4(adapter, MAC_REG_IDLO(mac->instance->index));

usr/src/uts/common/io/chxge/com/ch_mac.c

90

mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/ch_mac.c

94

mac_intr = t1_read_reg_4(mac->adapter,

usr/src/uts/common/io/chxge/com/ch_subr.c

1010

u32 pl_intr = t1_read_reg_4(adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/ch_subr.c

1088

u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE);

usr/src/uts/common/io/chxge/com/ch_subr.c

1104

u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);

usr/src/uts/common/io/chxge/com/ch_subr.c

1132

(void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */

usr/src/uts/common/io/chxge/com/ch_subr.c

1171

u32 val = t1_read_reg_4(adapter, A_TP_PC_CONFIG);

usr/src/uts/common/io/chxge/com/ch_subr.c

1250

u32 val = t1_read_reg_4(adapter, A_MC4_CFG);

usr/src/uts/common/io/chxge/com/ch_subr.c

129

*valp = t1_read_reg_4(adapter, A_TPI_RD_DATA);

usr/src/uts/common/io/chxge/com/ch_subr.c

205

u32 cause = t1_read_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE);

usr/src/uts/common/io/chxge/com/ch_subr.c

224

u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);

usr/src/uts/common/io/chxge/com/ch_subr.c

238

u32 tp_cause = t1_read_reg_4(adapter,

usr/src/uts/common/io/chxge/com/ch_subr.c

281

if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) {

usr/src/uts/common/io/chxge/com/ch_subr.c

288

*val = t1_read_reg_4(adapter, A_MI0_DATA_EXT);

usr/src/uts/common/io/chxge/com/ch_subr.c

300

if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) {

usr/src/uts/common/io/chxge/com/ch_subr.c

65

u32 val = t1_read_reg_4(adapter, reg) & mask;

usr/src/uts/common/io/chxge/com/cspi.c

48

*status = t1_read_reg_4(cspi->adapter, A_CSPI_INTR_STATUS);

usr/src/uts/common/io/chxge/com/espi.c

127

u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/espi.c

143

(void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);

usr/src/uts/common/io/chxge/com/espi.c

150

u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/espi.c

158

u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);

usr/src/uts/common/io/chxge/com/espi.c

172

(void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);

usr/src/uts/common/io/chxge/com/espi.c

297

espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL);

usr/src/uts/common/io/chxge/com/espi.c

355

sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);

usr/src/uts/common/io/chxge/com/espi.c

360

sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);

usr/src/uts/common/io/chxge/com/espi.c

391

*valp = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);

usr/src/uts/common/io/chxge/com/espi.c

83

status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);

usr/src/uts/common/io/chxge/com/espi.c

99

if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {

usr/src/uts/common/io/chxge/com/mc3.c

117

cause = t1_read_reg_4(adapter, cause_reg);

usr/src/uts/common/io/chxge/com/mc3.c

124

G_MC3_CE_ADDR(t1_read_reg_4(adapter, A_MC3_CE_ADDR)),

usr/src/uts/common/io/chxge/com/mc3.c

125

t1_read_reg_4(adapter, A_MC3_CE_DATA0),

usr/src/uts/common/io/chxge/com/mc3.c

126

t1_read_reg_4(adapter, A_MC3_CE_DATA1),

usr/src/uts/common/io/chxge/com/mc3.c

127

t1_read_reg_4(adapter, A_MC3_CE_DATA2),

usr/src/uts/common/io/chxge/com/mc3.c

128

t1_read_reg_4(adapter, A_MC3_CE_DATA3),

usr/src/uts/common/io/chxge/com/mc3.c

129

t1_read_reg_4(adapter, A_MC3_CE_DATA4));

usr/src/uts/common/io/chxge/com/mc3.c

137

G_MC3_UE_ADDR(t1_read_reg_4(adapter, A_MC3_UE_ADDR)),

usr/src/uts/common/io/chxge/com/mc3.c

138

t1_read_reg_4(adapter, A_MC3_UE_DATA0),

usr/src/uts/common/io/chxge/com/mc3.c

139

t1_read_reg_4(adapter, A_MC3_UE_DATA1),

usr/src/uts/common/io/chxge/com/mc3.c

140

t1_read_reg_4(adapter, A_MC3_UE_DATA2),

usr/src/uts/common/io/chxge/com/mc3.c

141

t1_read_reg_4(adapter, A_MC3_UE_DATA3),

usr/src/uts/common/io/chxge/com/mc3.c

142

t1_read_reg_4(adapter, A_MC3_UE_DATA4));

usr/src/uts/common/io/chxge/com/mc3.c

183

val = t1_read_reg_4(adapter, addr); /* flush */

usr/src/uts/common/io/chxge/com/mc3.c

184

if (!(t1_read_reg_4(adapter, addr) & F_BUSY))

usr/src/uts/common/io/chxge/com/mc3.c

200

val = t1_read_reg_4(adapter, A_MC3_CFG);

usr/src/uts/common/io/chxge/com/mc3.c

227

val = t1_read_reg_4(adapter, A_MC3_CFG);

usr/src/uts/common/io/chxge/com/mc3.c

229

val = t1_read_reg_4(adapter, A_MC3_CFG); /* flush */

usr/src/uts/common/io/chxge/com/mc3.c

232

val = t1_read_reg_4(adapter, A_MC3_STROBE);

usr/src/uts/common/io/chxge/com/mc3.c

248

val = t1_read_reg_4(adapter, A_MC3_STROBE);

usr/src/uts/common/io/chxge/com/mc3.c

275

val = t1_read_reg_4(adapter, A_MC3_REFRESH);

usr/src/uts/common/io/chxge/com/mc3.c

295

(void) t1_read_reg_4(adapter, A_MC3_REFRESH); /* flush */

usr/src/uts/common/io/chxge/com/mc3.c

305

(void) t1_read_reg_4(adapter, A_MC3_BIST_OP); /* flush */

usr/src/uts/common/io/chxge/com/mc3.c

310

val = t1_read_reg_4(adapter, A_MC3_BIST_OP);

usr/src/uts/common/io/chxge/com/mc3.c

318

val = t1_read_reg_4(adapter, A_MC3_CFG);

usr/src/uts/common/io/chxge/com/mc3.c

346

t1_read_reg_4(adapter, A_MC3_CFG));

usr/src/uts/common/io/chxge/com/mc3.c

46

u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc3.c

63

u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc3.c

88

old_en = t1_read_reg_4(mc3->adapter, A_MC3_INT_ENABLE);

usr/src/uts/common/io/chxge/com/mc4.c

100

val = t1_read_reg_4(adapter, A_MC4_STROBE);

usr/src/uts/common/io/chxge/com/mc4.c

113

val = t1_read_reg_4(adapter, A_MC4_STROBE);

usr/src/uts/common/io/chxge/com/mc4.c

121

val = t1_read_reg_4(adapter, A_MC4_STROBE);

usr/src/uts/common/io/chxge/com/mc4.c

143

val = t1_read_reg_4(adapter, A_MC4_REFRESH);

usr/src/uts/common/io/chxge/com/mc4.c

159

(void) t1_read_reg_4(adapter, A_MC4_REFRESH); /* flush */

usr/src/uts/common/io/chxge/com/mc4.c

169

(void) t1_read_reg_4(adapter, A_MC4_BIST_OP); /* flush */

usr/src/uts/common/io/chxge/com/mc4.c

174

val = t1_read_reg_4(adapter, A_MC4_BIST_OP);

usr/src/uts/common/io/chxge/com/mc4.c

182

val = t1_read_reg_4(adapter, A_MC4_CFG);

usr/src/uts/common/io/chxge/com/mc4.c

184

val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */

usr/src/uts/common/io/chxge/com/mc4.c

217

pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc4.c

230

pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc4.c

247

u32 cause = t1_read_reg_4(adapter, A_MC4_INT_CAUSE);

usr/src/uts/common/io/chxge/com/mc4.c

254

G_MC4_CE_ADDR(t1_read_reg_4(adapter, A_MC4_CE_ADDR)),

usr/src/uts/common/io/chxge/com/mc4.c

255

t1_read_reg_4(adapter, A_MC4_CE_DATA0),

usr/src/uts/common/io/chxge/com/mc4.c

256

t1_read_reg_4(adapter, A_MC4_CE_DATA1),

usr/src/uts/common/io/chxge/com/mc4.c

257

t1_read_reg_4(adapter, A_MC4_CE_DATA2),

usr/src/uts/common/io/chxge/com/mc4.c

258

t1_read_reg_4(adapter, A_MC4_CE_DATA3),

usr/src/uts/common/io/chxge/com/mc4.c

259

t1_read_reg_4(adapter, A_MC4_CE_DATA4));

usr/src/uts/common/io/chxge/com/mc4.c

267

G_MC4_UE_ADDR(t1_read_reg_4(adapter, A_MC4_UE_ADDR)),

usr/src/uts/common/io/chxge/com/mc4.c

268

t1_read_reg_4(adapter, A_MC4_UE_DATA0),

usr/src/uts/common/io/chxge/com/mc4.c

269

t1_read_reg_4(adapter, A_MC4_UE_DATA1),

usr/src/uts/common/io/chxge/com/mc4.c

270

t1_read_reg_4(adapter, A_MC4_UE_DATA2),

usr/src/uts/common/io/chxge/com/mc4.c

271

t1_read_reg_4(adapter, A_MC4_UE_DATA3),

usr/src/uts/common/io/chxge/com/mc4.c

272

t1_read_reg_4(adapter, A_MC4_UE_DATA4));

usr/src/uts/common/io/chxge/com/mc4.c

311

val = t1_read_reg_4(adap, A_MC4_BD_OP);

usr/src/uts/common/io/chxge/com/mc4.c

313

val = t1_read_reg_4(adap, A_MC4_BD_OP);

usr/src/uts/common/io/chxge/com/mc4.c

318

buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA3);

usr/src/uts/common/io/chxge/com/mc4.c

320

buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA2);

usr/src/uts/common/io/chxge/com/mc4.c

322

buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA1);

usr/src/uts/common/io/chxge/com/mc4.c

323

buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA0);

usr/src/uts/common/io/chxge/com/mc4.c

49

u32 mc4_cfg = t1_read_reg_4(adapter, A_MC4_CFG);

usr/src/uts/common/io/chxge/com/mc4.c

67

val = t1_read_reg_4(adapter, addr); /* flush */

usr/src/uts/common/io/chxge/com/mc4.c

69

if (!(t1_read_reg_4(adapter, addr) & F_BUSY))

usr/src/uts/common/io/chxge/com/mc4.c

89

val = t1_read_reg_4(adapter, A_MC4_CFG);

usr/src/uts/common/io/chxge/com/mc4.c

91

val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */

usr/src/uts/common/io/chxge/com/mc5.c

147

return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX);

usr/src/uts/common/io/chxge/com/mc5.c

167

return t1_read_reg_4(mc5->adapter, A_MC5_SERVER_INDEX);

usr/src/uts/common/io/chxge/com/mc5.c

194

*v1 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA0);

usr/src/uts/common/io/chxge/com/mc5.c

195

*v2 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA1);

usr/src/uts/common/io/chxge/com/mc5.c

196

*v3 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA2);

usr/src/uts/common/io/chxge/com/mc5.c

410

cfg = t1_read_reg_4(adap, A_MC5_CONFIG) & ~F_MODE;

usr/src/uts/common/io/chxge/com/mc5.c

518

u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc5.c

536

u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/mc5.c

563

u32 cause = t1_read_reg_4(adap, A_MC5_INT_CAUSE);

usr/src/uts/common/io/chxge/com/mc5.c

646

cfg = t1_read_reg_4(adapter, A_MC5_CONFIG);

usr/src/uts/common/io/chxge/com/mc5.c

694

u32 cfg = t1_read_reg_4(mc5->adapter, A_MC5_CONFIG);

usr/src/uts/common/io/chxge/com/pm3393.c

165

pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/pm3393.c

247

pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE);

usr/src/uts/common/io/chxge/com/tp.c

122

tp_scnt = t1_read_reg_4(adapter, A_TP_SHIFT_CNT);

usr/src/uts/common/io/chxge/com/tp.c

139

val = t1_read_reg_4(tp->adapter, A_TP_PARA_REG3);

usr/src/uts/common/io/chxge/com/tp.c

167

*data++ = t1_read_reg_4(adap, A_TP_MIB_DATA);

usr/src/uts/common/io/chxge/com/tp.c

266

val = t1_read_reg_4(ap, A_TP_PC_CONFIG);

usr/src/uts/common/io/chxge/com/tp.c

317

u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/tp.c

338

u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/tp.c

379

cause = t1_read_reg_4(tp->adapter, A_TP_INT_CAUSE);

usr/src/uts/common/io/chxge/com/tp.c

386

u32 val = t1_read_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG);

usr/src/uts/common/io/chxge/com/tp.c

91

u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION);

usr/src/uts/common/io/chxge/com/tp.c

98

u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION);

usr/src/uts/common/io/chxge/com/ulp.c

45

u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/ulp.c

64

u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/com/ulp.c

74

u32 cause = t1_read_reg_4(ulp->adapter, A_ULP_INT_CAUSE);

usr/src/uts/common/io/chxge/glue.c

222

pe->pe_reg_val = reg = t1_read_reg_4(chp, pe->addr);

usr/src/uts/common/io/chxge/glue.c

240

reg = t1_read_reg_4(chp, pe->addr);

usr/src/uts/common/io/chxge/pe.c

1520

enable = t1_read_reg_4(adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/pe.c

1531

u32 enable = t1_read_reg_4(adapter, A_PL_ENABLE);

usr/src/uts/common/io/chxge/sge.c

1136

u32 irq_reg = t1_read_reg_4(sge->obj, A_SG_INT_ENABLE);

usr/src/uts/common/io/chxge/sge.c

288

status = t1_read_reg_4(sge->obj, A_SG_INT_CAUSE);

usr/src/uts/common/io/chxge/sge.c

506

u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE);

usr/src/uts/common/io/chxge/sge.c

523

u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE);

usr/src/uts/common/io/chxge/sge.c

550

u32 cause = t1_read_reg_4(obj, A_SG_INT_CAUSE);