DMA_ENDVMA
fas->f_dma_csr &= ~DMA_ENDVMA;
ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
DMA_WRITE | DMA_ENDVMA | DMA_DSBL_DRAIN; \
ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
DMA_WRITE | DMA_ENDVMA | DMA_DSBL_DRAIN; \
ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
(fas->f_dma_csr & ~DMA_WRITE) | DMA_ENDVMA | DMA_DSBL_DRAIN; \
fas->f_dma_csr &= ~(DMA_ENDVMA | DMA_WRITE);
fas->f_dma_csr &= ~(DMA_ENDVMA | DMA_WRITE);