shmem2_region_t
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,size), &shmem2_size);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,size), &shmem2_size);
const u32_t mcp_dcbx_neg_res_offset = OFFSETOF(shmem2_region_t,dcbx_neg_res_offset);
const u32_t mcp_dcbx_remote_mib_offset = OFFSETOF(shmem2_region_t,dcbx_remote_mib_offset);
const u32_t field_res_ext_offset = OFFSETOF(shmem2_region_t,dcbx_neg_res_ext_offset);
const u32_t mcp_dcbx_lldp_params_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_params_offset);
const u32_t mcp_dcbx_lldp_dcbx_stat_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_dcbx_stat_offset);
const u32_t mcp_dcbx_lldp_params_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_params_offset);
const u32_t mcp_dcbx_lldp_dcbx_stat_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_dcbx_stat_offset);
const u32_t dcbx_lldp_params_field_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_params_offset);
const u32_t drv_flags_offset = OFFSETOF(shmem2_region_t,drv_flags);
const u32_t drv_flags_offset = OFFSETOF(shmem2_region_t,drv_flags);
const u32_t mcp_lldp_params_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_params_offset);
const u32_t dcbx_en_offset = OFFSETOF(shmem2_region_t,dcbx_en[port]);
const u32_t mcp_dcbx_lldp_params_offset = OFFSETOF(shmem2_region_t,dcbx_lldp_params_offset);
offset = OFFSETOF(shmem2_region_t,ibft_host_addr);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,size), &shmem2_size);
if (shmem2_size > OFFSETOF(shmem2_region_t,mf_cfg_addr))
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,mf_cfg_addr), &mf_cfg_offset_value);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t, lfa_host_addr[port]), &pdev->params.link.lfa_base);
u32_t drv_ver_offset = OFFSETOF(shmem2_region_t,func_os_drv_ver);
LM_SHMEM2_READ (pdev, OFFSETOF(shmem2_region_t,size), &shmem2_size);
shmem2_region_t* shmem2_region_dummy = NULL;
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t, drv_info_control), &val );
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_info_host_addr_lo), pdev->vars.stats.stats_collect.drv_info_to_mfw.drv_info_to_mfw_phys_addr.as_u32.low );
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_info_host_addr_hi), pdev->vars.stats.stats_collect.drv_info_to_mfw.drv_info_to_mfw_phys_addr.as_u32.high );
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,mcp_vf_disabled[i]), &mcp_vf_disabled[i]);
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t,drv_ack_vf_disabled[FUNC_MAILBOX_ID(pdev)][i]), mcp_vf_disabled[i]);
offset = OFFSETOF(shmem2_region_t, size);
offset = OFFSETOF(shmem2_region_t, ncsi_oem_data_addr);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem_base_addr), &shmem_base[1]);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem2_base_addr), &shmem_base2[1]);
temp = OFFSETOF( shmem2_region_t, dcc_support);
LM_SHMEM2_WRITE(pdev, OFFSETOF( shmem2_region_t, afex_driver_support),
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_capabilities_flag[FUNC_MAILBOX_ID(pdev)]), DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED);
LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_capabilities_flag[func_mb_id]), DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | (pdev->params.mtu_max << DRV_FLAGS_MTU_SHIFT));
const u32_t shmem_offset = OFFSETOF(shmem2_region_t, drv_capabilities_flag[func_mb_id]);
const u32_t offset = OFFSETOF(shmem2_region_t, afex_scratchpad_addr_to_write[func_mailbox_id]);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem_base_addr), &shmem_base[1]);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem2_base_addr), &shmem_base2[1]);
u32_t offset = OFFSETOF(shmem2_region_t, edebug_driver_if[1]);
LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t, size), &shmem2_size);