serdes_digital_reg_t
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_stat1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),