usr/src/uts/common/disp/disp.c

1057

ASSERT(getpil() >= DISP_LEVEL);

usr/src/uts/common/disp/disp_lock.c

86

lock_set_spl(lp, ipltospl(DISP_LEVEL), &curthread->t_oldspl);

usr/src/uts/common/disp/fx.c

1830

return ((void *)(uintptr_t)__ipltospl(DISP_LEVEL));

usr/src/uts/common/disp/thread.c

177

mutex_init(&reaplock, NULL, MUTEX_SPIN, (void *)ipltospl(DISP_LEVEL));

usr/src/uts/common/os/cpu.c

575

getpil() >= DISP_LEVEL) {

usr/src/uts/common/os/cpu.c

708

getpil() >= DISP_LEVEL);

usr/src/uts/common/os/cpu.c

711

getpil() >= DISP_LEVEL)

usr/src/uts/common/os/softint.c

216

ASSERT(getpil() >= DISP_LEVEL);

usr/src/uts/i86pc/ml/genassym.c

75

printf("#define\tDISP_LEVEL 0x%x\n", DISP_LEVEL);

usr/src/uts/i86pc/os/cpupm/cpupm_mach.c

504

(void *)ipltospl(DISP_LEVEL));

usr/src/uts/i86pc/os/pci_cfgspace.c

117

(ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));

usr/src/uts/i86pc/os/trap.c

1558

if (getpil() >= DISP_LEVEL) {

usr/src/uts/intel/io/acpica/acpica.c

148

(ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));

usr/src/uts/intel/os/desctbls.c

1131

ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL);

usr/src/uts/intel/os/desctbls.c

1186

ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL);

usr/src/uts/intel/os/sundep.c

654

ASSERT(curthread->t_preempt != 0 || getpil() >= DISP_LEVEL);

usr/src/uts/sfmmu/vm/hat_sfmmu.c

1624

(void *)ipltospl(DISP_LEVEL));

usr/src/uts/sparc/dtrace/dtrace_isa.c

341

dtrace_getipl() > DISP_LEVEL);

usr/src/uts/sun4/os/trap.c

1865

getpil()) >= DISP_LEVEL) {

usr/src/uts/sun4u/cpu/us3_common.c

3006

ASSERT(curthread->t_preempt > 0 || getpil() >= DISP_LEVEL);

usr/src/uts/sun4v/pcbe/niagara2_pcbe.c

424

ASSERT(getpil() >= DISP_LEVEL);