rir
const imc_rank_ileave_t *rir = NULL;
rir = &chan->ich_rankileaves[i];
if (rir->irle_enabled && dec->ids_chanaddr >= base &&
dec->ids_chanaddr < rir->irle_limit) {
base = rir->irle_limit;
if (rir == NULL || i == chan->ich_nrankileaves) {
dec->ids_rir = rir;
index = (dec->ids_chanaddr >> shift) % rir->irle_nways;
if (index >= rir->irle_nentries) {
rirtarg = &rir->irle_entries[index];
rankaddr /= rir->irle_nways;
nvlist_t **dimms, **rir;
nvlist_lookup_nvlist_array(nvl, "ich_rankileaves", &rir,
if (nvlist_lookup_boolean_value(rir[i], "irle_enabled",
nvlist_lookup_uint8(rir[i], "irle_nways",
nvlist_lookup_uint8(rir[i], "irle_nwaysbits",
nvlist_lookup_uint64(rir[i], "irle_limit",
nvlist_lookup_nvlist_array(rir[i], "irle_entries",
rank = rir[i][j][k].way[0].dimm_rank;
if (rank == rir[i][j][k].way[1].dimm_rank &&
rank == rir[i][j][k].way[2].dimm_rank &&
rank == rir[i][j][k].way[3].dimm_rank) {
rir[i][j][k].interleave = 1;
(rank == rir[i][j][k].way[1].dimm_rank ||
rank == rir[i][j][k].way[2].dimm_rank ||
rank == rir[i][j][k].way[3].dimm_rank) {
rir[i][j][k].interleave = 2;
rir[i][j][k].interleave = 4;
rir[i][j][k].way[l].dimm_rank,
((rir[i][j][k].way[l].soffset +
rir[i][j][k].interleave));
base = rir[i][j][k].limit;
if (caddr >= base && caddr < rir[node][channel][i].limit) {
rir[node][channel][i].way[way].offset *
rir[node][channel][i].interleave) &
rir[node][channel][i].way[way].offset *
rir[node][channel][i].interleave) &
rank = rir[node][channel][i].way[way].rank;
base = rir[node][channel][i].limit;
if (rir[node][channel][i].way[way].dimm_rank == rank) {
rlimit = rir[node][channel][i].way[way].rlimit;
rir[node][channel][i].interleave -
(int64_t)rir[node][channel][i].
rir[node][channel][i].interleave -
(int64_t)rir[node][channel][i].
if (caddr < rir[node][channel][i].limit) {
rir[node][channel][i].interleave;
rank_sz = (rir[node][channel][i].limit -
rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
base = rir[node][channel][i].limit;
if (rir[socket][channel][k].way[l].dimm_rank == rank &&
rir[socket][channel][k].way[l].rlimit == 0) {
rir[socket][channel][k].way[l].rlimit =
if (rir[socket][channel][k].way[l].dimm_rank == rank &&
rir[socket][channel][k].way[l].rlimit == 0) {
rir[socket][channel][k].way[l].rlimit = rank_addr;
rir[i][j][k].limit = RIR_LIMIT(rir_limit);
rir[i][j][k].way[l].offset =
rir[i][j][k].way[l].soffset =
rir[i][j][k].way[l].rank =
rir[i][j][k].way[l].dimm =
rir[i][j][k].way[l].dimm_rank =
rir[i][j][k].way[l].rlimit = 0;
extern rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]