regvalue
list_append(parts, regvalue(matches[j], string));
if ((s = regvalue(matches[1], line)) == NULL)
if ((s = regvalue(matches[4], line)) == NULL)
if ((s = regvalue(matches[7], line)) == NULL)
if ((s = regvalue(matches[8], line)) == NULL)
if ((s = regvalue(matches[1], line)) == NULL)
if ((s = regvalue(matches[2], line)) == NULL)
if ((s = regvalue(matches[3], line)) == NULL)
if ((s = regvalue(matches[4], line)) == NULL)
if ((s = regvalue(matches[1], line)) == NULL)
if ((s = regvalue(matches[2], line)) == NULL)
if ((s = regvalue(matches[3], line)) == NULL)
static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue,
cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset)
size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1;
size = (~(PCI_BASE_M_ADDR_M & regvalue))+1;
if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) {
if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) {
} else if ((PCI_BASE_TYPE_M & regvalue)
u32 i, regvalue = 0;
regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
E1000_WRITE_REG(hw, reg, regvalue);
regvalue = E1000_READ_REG(hw, reg);
if (regvalue & E1000_GEN_CTL_READY)
if (!(regvalue & E1000_GEN_CTL_READY)) {
pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset)
size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1;
size = (~(PCI_BASE_M_ADDR_M & regvalue))+1;
if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) {
if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) {
} else if ((PCI_BASE_TYPE_M & regvalue)
if (regvalue & PCI_BASE_PREF_M)
pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset)
size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1;
size = (~(PCI_BASE_M_ADDR_M & regvalue))+1;
if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) {
if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) {
} else if ((PCI_BASE_TYPE_M & regvalue)