reg_space_t
((u32_t) (((u8_t *) &(((reg_space_t *) 0)->_field)) - ((u8_t *) 0)))
cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]);
cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode);
cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state);
cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]);
cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask);
cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter);
cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction);
cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint);
cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]);
OFFSETOF(reg_space_t, com.com_comxq_ftq_ctl),
OFFSETOF(reg_space_t, com.com_comtq_ftq_ctl),
OFFSETOF(reg_space_t, com.com_comq_ftq_ctl),
OFFSETOF(reg_space_t, cp.cp_cpq_ftq_ctl),
OFFSETOF(reg_space_t, mcp.mcp_mcpq_ftq_ctl),
OFFSETOF(reg_space_t, rxp.rxp_cftq_ctl),
OFFSETOF(reg_space_t, rxp.rxp_ftq_ctl),
OFFSETOF(reg_space_t, tas.tas_ftq_ctl),
OFFSETOF(reg_space_t, tpat.tpat_ftq_ctl),
OFFSETOF(reg_space_t, txp.txp_ftq_ctl),
OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_addr_l),
OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_addr_h),
OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_data),
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t, pci_config.pcicfg_pcix_cap_id),
OFFSETOF(reg_space_t, pci_config.pcicfg_pcix_cap_id),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(tcp_syn_dos_defense),
OFFSETOF(reg_space_t, rbuf.rbuf_config),
OFFSETOF(reg_space_t, rbuf.rbuf_config2),
OFFSETOF(reg_space_t, rbuf.rbuf_config3),
OFFSETOF(reg_space_t, rbuf.rbuf_command),
OFFSETOF(reg_space_t, rbuf.rbuf_command),
OFFSETOF(reg_space_t, rbuf.rbuf_config3),
OFFSETOF(reg_space_t, rbuf.rbuf_cu_buffer_size),
OFFSETOF(reg_space_t, rbuf.rbuf_cu_buffer_size),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_buf_size),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(cu_rate_limiter_enable),
OFFSETOF(reg_space_t, txp.txp_scratch[0])+TXP_HSI_OFFSETOFF(cu_rate_limiter_enable),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(cu_rate_limiter_enable),
REG_WR_IND(pdev, OFFSETOF(reg_space_t, cp.cp_scratch[0])+CP_HSI_OFFSETOFF(fw_doorbell), 1);
REG_WR_IND(pdev, OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(fw_doorbell), 1);
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(catchup_overide),
REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val);
OFFSETOF(reg_space_t, rbuf.rbuf_command),
OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_alloc),
REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val);
REG_WR_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_free), val);
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_device_control),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(enable_fast_iscsi_response),
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t,
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_unicast_no_buffer),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_mcast_no_buffer),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_bcast_no_buffer),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_unicast_no_buffer),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_mcast_no_buffer),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_bcast_no_buffer),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_unicast_bytes_rcvd)+4,
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_unicast_bytes_rcvd),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_multicast_bytes_rcvd)+4,
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_multicast_bytes_rcvd),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_broadcast_bytes_rcvd)+4,
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_broadcast_bytes_rcvd),
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(unicast_bytes_xmit)+4,
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(unicast_bytes_xmit),
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(multicast_bytes_xmit)+4,
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(multicast_bytes_xmit),
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(broadcast_bytes_xmit)+4,
OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(broadcast_bytes_xmit),
OFFSETOF(reg_space_t, tas.tas_thbuf[(j-1) * 2]),
OFFSETOF(reg_space_t, tas.tas_thbuf[(j-1) * 2 + 1]),
OFFSETOF(reg_space_t, tas.tas_thbuf[(j+1) * 2]),
OFFSETOF(reg_space_t, tas.tas_thbuf[(j+1) * 2 + 1]),
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),
OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+ctx_offset,
OFFSETOF(reg_space_t, pci_config.pcicfg_vendor_id),
OFFSETOF(reg_space_t, pci_config.pcicfg_subsystem_vendor_id),
OFFSETOF(reg_space_t, pci_config.pcicfg_int_line),
OFFSETOF(reg_space_t, pci_config.pcicfg_cache_line_size),
OFFSETOF(reg_space_t, pci_config.pcicfg_class_code),
OFFSETOF(reg_space_t, pci_config.pcicfg_bar_1),
OFFSETOF(reg_space_t, pci_config.pcicfg_bar_2),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_misc_config),
OFFSETOF(reg_space_t, pci.pci_config_2));
pdev->vars.regview = (reg_space_t *) mm_map_io_base(
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
OFFSETOF(reg_space_t, pci_config.pcicfg_command),
REG_RD_IND(pdev, OFFSETOF(reg_space_t, mcp.mcp_toe_id), &val);
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_host_bseq),
OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_host_bseq),
OFFSETOF(reg_space_t, _name), \
LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \
if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \
LOG_REG_RD(_pdev, OFFSETOF(reg_space_t, _name), *(_ret))
LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \
if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \
OFFSETOF(reg_space_t, _name), \
LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \
if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \
(UINT64)(OFFSETOF(reg_space_t, _name)), \
(UINT64)(OFFSETOF(reg_space_t, _name)), \
if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \
(UINT64)(OFFSETOF(reg_space_t, _name)), \
(UINT64)(OFFSETOF(reg_space_t, _name)), \
volatile reg_space_t *regview;
REG_WR_IND(lmdevice, (OFFSETOF(reg_space_t, tpat.tpat_scratch[0]) +
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),
OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr),