rdmsr
uint64_t rdmsr(u_int msr);
uint64_t rdmsr(u_int msr);
extern void rdmsr(uint32_t, uint64_t *);
if (kmt_rwmsr(addr, &val, rdmsr) < 0) {
uint64_t rdmsr(uint32_t);
wrmsr(0x1B, rdmsr(0x1B) & ~APICBASE_ENABLED);
wrmsr(0x1B, rdmsr(0x1B) | APICBASE_ENABLED);
uint64_t tsc = rdmsr(MSR_TSC);
uint64_t base = rdmsr(MSR_APICBASE);
uint64_t base = rdmsr(MSR_APICBASE);
val = rdmsr(msr);
(void) rdmsr(MSR_APICBASE);
crm.cr_msr_val = rdmsr(crm.cr_msr_nr);
return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2)));
apic_base_msr = rdmsr(REG_APIC_BASE_MSR);
i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff);
tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2));
apic_base_msr = rdmsr(REG_APIC_BASE_MSR);
ticks = rdmsr(IA32_DEADLINE_TSC_MSR);
reg = rdmsr(IA32_CLOCK_MODULATION_MSR);
reg = rdmsr(IA32_CLOCK_MODULATION_MSR);
reg = rdmsr(IA32_PERF_CTL_MSR);
mcnt = rdmsr(IA32_MPERF_MSR);
acnt = rdmsr(IA32_APERF_MSR);
mcnt = rdmsr(IA32_MPERF_MSR);
acnt = rdmsr(IA32_APERF_MSR);
nb_cfg_reg = rdmsr(MSR_AMD_NB_CFG);
old = (uintptr_t)rdmsr(MSR_AMD_GSBASE);
*value = rdmsr(msr);
uint64_t rv = rdmsr(msr);
rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
(((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
wrmsr(MSR_AMD_NB_CFG, rdmsr(MSR_AMD_NB_CFG) | AMD_GH_NB_CFG_EN_ECS);
printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE),
rdmsr; \
rdmsr; \
case REG_FSBASE: return (rdmsr(MSR_AMD_FSBASE));
case REG_GSBASE: return (rdmsr(MSR_AMD_GSBASE));
umc->umc_tom = rdmsr(MSR_AMD_TOM);
umc->umc_tom2 = rdmsr(MSR_AMD_TOM2);
gctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);
host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
vmcs->identifier = VMX_BASIC_REVISION(rdmsr(MSR_VMX_BASIC));
vmcs_write(VMCS_HOST_IA32_SYSENTER_ESP, rdmsr(MSR_SYSENTER_ESP_MSR));
SDT_PROBE_DEFINE4(vmm, vmx, exit, rdmsr,
vmxctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);
uint64_t ept_caps = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
fixed0 = rdmsr(MSR_VMX_CR0_FIXED0);
fixed1 = rdmsr(MSR_VMX_CR0_FIXED1);
fixed0 = rdmsr(MSR_VMX_CR4_FIXED0);
fixed1 = rdmsr(MSR_VMX_CR4_FIXED1);
rdmsr(MSR_SYSENTER_EIP_MSR));
val = rdmsr(ctl_reg);
trueval = rdmsr(true_ctl_reg); /* step c */
misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
guest_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
guest_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
guest_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
guest_msrs[IDX_MSR_KGSBASE] = rdmsr(MSR_KGSBASE);
true_ctls_avail = (rdmsr(MSR_VMX_BASIC) & (1UL << 55)) != 0;
return (rdmsr(MSR_FSBASE));
vmm_host_efer = rdmsr(MSR_EFER);
vmm_host_pat = rdmsr(MSR_PAT);
return (rdmsr(MSR_GSBASE));
uint64_t ept_caps = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
val = rdmsr(MSR_IA32_SPEC_CTRL);
val = rdmsr(MSR_IA32_SPEC_CTRL);
val = rdmsr(MSR_AMD_EFER);
val = rdmsr(MSR_AMD_CPUID7_FEATURES);
val = rdmsr(MSR_IA32_TSX_CTRL);
val = rdmsr(MSR_IA32_TSX_CTRL);
reg = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
value = rdmsr(MSR_PLATFORM_INFO);
val = rdmsr(MSR_AMD_DE_CFG);
val = rdmsr(MSR_AMD_DE_CFG);
osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
return (rdmsr(MSR_AMD_OSVW_STATUS +
reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
fctrl = rdmsr(MSR_IA32_FEAT_CTRL);
msr = rdmsr(MSR_IA32_VMX_BASIC);
msr = rdmsr(query_true_ctl ?
msr = rdmsr(MSR_IA32_VMX_PROCBASED2_CTLS);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
msr = rdmsr(MSR_IA32_FEAT_CTRL);
const uint64_t evtsel = rdmsr(MSR_CPC_EXTD_EVTSEL(i));
rdmsr(MSR_CPC_EXTD_CTR(i));
cpc_state->hscs_regs[i].hc_ctr = rdmsr(MSR_CPC_EXTD_CTR(i));
efer = rdmsr(MSR_AMD_EFER);
msr = rdmsr(MSR_AMD_VM_CR);
uinfop->cui_rev = rdmsr(MSR_AMD_PATCHLEVEL);
uinfop->cui_rev = (rdmsr(MSR_INTC_UCODE_REV) >> INTC_UCODE_REV_SHIFT);
uinfop->cui_platid = 1 << ((rdmsr(MSR_INTC_PLATFORM_ID) >>
curpic = rdmsr(cfg->core_pmc);
(value) = rdmsr((msr)); \
DTRACE_PROBE2(rdmsr, uint64_t, (msr), uint64_t, (value));
curpic[i] = rdmsr(opd.opd_picf(i));
curpic[i] = rdmsr(p4_ctrs[i].pc_caddr);
if (rdmsr(p4_ctrs[i].pc_ctladdr) & CCCR_OVF)
extern uint64_t rdmsr(uint_t);