ql_write_reg
ql_write_reg(qlge, REG_RSVD7, 0xfeed0002);
ql_write_reg(qlge, REG_RSVD7, 0xfeed0003);
ql_write_reg(qlge, REG_RSVD7, 0xfeed0004);
ql_write_reg(qlge, REG_RSVD7, 0xfeed0003);
ql_write_reg(qlge, REG_RSVD7, 0xfeed0004);
ql_write_reg(qlge, REG_ICB_ACCESS_ADDRESS_LOWER, LS_64BITS(phy_addr));
ql_write_reg(qlge, REG_ICB_ACCESS_ADDRESS_UPPER, MS_64BITS(phy_addr));
ql_write_reg(qlge, REG_CONFIGURATION, (mask | value));
ql_write_reg(qlge, REG_MAC_PROTOCOL_ADDRESS_INDEX /* A8 */, data1);
ql_write_reg(qlge, REG_MAC_PROTOCOL_DATA /* 0xAC */, data2);
ql_write_reg(qlge, REG_XGMAC_ADDRESS, addr|XGMAC_ADDRESS_READ_TRANSACT);
ql_write_reg(qlge, REG_SEMAPHORE, sem_bits | sem_mask);
ql_write_reg(qlge, REG_SEMAPHORE, sem_mask);
ql_write_reg(qlge, REG_MAC_PROTOCOL_ADDRESS_INDEX,
ql_write_reg(qlge, REG_MAC_PROTOCOL_DATA, lower);
ql_write_reg(qlge, REG_MAC_PROTOCOL_ADDRESS_INDEX,
ql_write_reg(qlge, REG_MAC_PROTOCOL_DATA, upper);
ql_write_reg(qlge, REG_MAC_PROTOCOL_ADDRESS_INDEX,
ql_write_reg(qlge, REG_MAC_PROTOCOL_DATA,
ql_write_reg(qlge, REG_ROUTING_INDEX, value);
ql_write_reg(qlge, REG_ROUTING_DATA, enable ? mask : 0);
ql_write_reg(qlge, REG_SYSTEM, mask | value);
ql_write_reg(qlge, REG_NIC_RECEIVE_CONFIGURATION, mask | value);
ql_write_reg(qlge, REG_INTERRUPT_MASK, (INTR_MASK_PI << 16)
ql_write_reg(qlge, REG_SPLIT_HEADER, SMALL_BUFFER_SIZE);
ql_write_reg(qlge, REG_FUNCTION_SPECIFIC_CONTROL, mask | value);
ql_write_reg(qlge, REG_RESET_FAILOVER, FUNCTION_RESET_MASK
ql_write_reg(qlge, REG_INTERRUPT_ENABLE,
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, (INTR_EN_EI << 16));
ql_write_reg(qlge, REG_INTERRUPT_MASK,
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, ctx->intr_en_mask);
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, ctx->intr_en_mask);
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, ctx->intr_dis_mask);
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, ctx->intr_dis_mask);
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, ctx->intr_dis_mask);
ql_write_reg(qlge, reg->addr, reg->value);
ql_write_reg(qlge, REG_HOST_CMD_STATUS, CSR_CMD_CLR_PAUSE);
ql_write_reg(qlge, REG_HOST_CMD_STATUS, CSR_CMD_SET_PAUSE);
ql_write_reg(qlge, REG_INTERRUPT_ENABLE, 0x037f0300 + i);
ql_write_reg(qlge, REG_XG_SERDES_ADDR, reg | PROC_ADDR_R);
ql_write_reg(qlge, REG_PRB_MX_ADDR, probe);
ql_write_reg(qlge, REG_PRB_MX_ADDR, probe);
ql_write_reg(qlge, REG_ROUTING_INDEX, val);
ql_write_reg(qlge,
ql_write_reg(qlge, REG_NIC_ENHANCED_TX_SCHEDULE,
ql_write_reg(qlge, REG_CNA_ENHANCED_TX_SCHEDULE,
ql_write_reg(qlge, i, (data | (data << 16)));
ql_write_reg(qlge, REG_FLASH_ADDRESS, faddr | FLASH_R_FLAG);
ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
ql_write_reg(qlge, REG_FLASH_DATA, data);
ql_write_reg(qlge, REG_FLASH_ADDRESS, cmd);
ql_write_reg(qlge, REG_FLASH_DATA, data);
ql_write_reg(qlge, REG_FLASH_ADDRESS, addr);
ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);
ql_write_reg(qlge, REG_HOST_CMD_STATUS, HOST_CMD_SET_RISC_RESET);
ql_write_reg(qlge, REG_HOST_CMD_STATUS, HOST_CMD_CLEAR_RISC_RESET);
ql_write_reg(qlge, REG_PROCESSOR_DATA, mbx_cmd->mb[i]);
ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);
ql_write_reg(qlge, REG_HOST_CMD_STATUS, HOST_CMD_SET_RISC_INTR);
ql_write_reg(qlge, REG_HOST_CMD_STATUS,
ql_write_reg(qlge, REG_HOST_CMD_STATUS,
ql_write_reg(qlge, REG_HOST_CMD_STATUS,
ql_write_reg(qlge, REG_PROCESSOR_DATA, data);
ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);
extern void ql_write_reg(qlge_t *, uint32_t, uint32_t);