ql_build_coredump_seg_header
ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr,
ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->xgmac_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->code_ram_seg_hdr,
ql_build_coredump_seg_header(&mpi_coredump->memc_ram_seg_hdr,