usr/src/uts/intel/sys/amdzen/df.h

1004

#define DF_FIDMASK2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1050

#define DF_CCD_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1073

#define DF_PHYS_CORE_EN0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1077

#define DF_PHYS_CORE_EN1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1081

#define DF_PHYS_CORE_EN2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1085

#define DF_PHYS_CORE_EN3_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1089

#define DF_PHYS_CORE_EN4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1093

#define DF_PHYS_CORE_EN5_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

112

#define DF_REV_ALL (DF_REV_ALL_23 | DF_REV_ALL_4)

usr/src/uts/intel/sys/amdzen/df.h

1137

#define DF_FICAA_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1164

#define DF_FICAD_LO_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1168

#define DF_FICAD_HI_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1211

#define DF_SYS_FUN_FID1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

1227

#define DF_SYS_FUN_FID2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

383

#define DF_CFG_ADDR_CTL_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

412

#define DF_CFGMAP_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

416

#define DF_CFGMAP_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

438

#define DF_IO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

467

#define DF_IO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

498

#define DF_DRAM_HOLE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

710

#define DF_DRAM_OFFSET_V4(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

728

#define DF_VGA_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

745

#define DF_ECAM_BASE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

749

#define DF_ECAM_BASE_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

753

#define DF_ECAM_LIMIT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

757

#define DF_ECAM_LIMIT_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

783

#define DF_MMIO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

787

#define DF_MMIO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

799

#define DF_MMIO_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

833

#define DF_MMIO_EXT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

905

#define DF_SYSCFG_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

927

#define DF_COMPCNT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

984

#define DF_FIDMASK0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \

usr/src/uts/intel/sys/amdzen/df.h

994

#define DF_FIDMASK1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \