usr/src/uts/intel/sys/amdzen/df.h

112

#define DF_REV_ALL (DF_REV_ALL_23 | DF_REV_ALL_4)

usr/src/uts/intel/sys/amdzen/df.h

1132

#define DF_FICAA_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

1156

#define DF_FICAD_LO_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

1160

#define DF_FICAD_HI_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

230

#define DF_FBIINFO1 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \

usr/src/uts/intel/sys/amdzen/df.h

242

#define DF_FBIINFO2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \

usr/src/uts/intel/sys/amdzen/df.h

379

#define DF_CFG_ADDR_CTL_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

394

#define DF_CFGMAP_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

434

#define DF_IO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

463

#define DF_IO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

494

#define DF_DRAM_HOLE_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

518

#define DF_DRAM_BASE_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

559

#define DF_DRAM_LIMIT_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

706

#define DF_DRAM_OFFSET_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

724

#define DF_VGA_EN_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

775

#define DF_MMIO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

779

#define DF_MMIO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

795

#define DF_MMIO_CTL_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \

usr/src/uts/intel/sys/amdzen/df.h

919

#define DF_COMPCNT_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \