usr/src/common/mc/zen_umc/zen_umc_decode.c

434

umc->umc_df_rev >= DF_REV_4D2) {

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_np2_k.c

210

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_np2_k.c

36

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_np2_k.c

519

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_np2_k.c

780

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_nps_k.c

35

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_nps_k.c

813

.umc_df_rev = DF_REV_4D2,

usr/src/test/os-tests/tests/zen_umc/zen_umc_test_nps_k.c

947

.umc_df_rev = DF_REV_4D2,

usr/src/uts/intel/io/amdzen/amdzen.c

1094

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/amdzen.c

1189

if (df->adf_rev == DF_REV_4D2) {

usr/src/uts/intel/io/amdzen/amdzen.c

1231

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/amdzen.c

1321

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/amdzen.c

2467

if (df->adf_rev >= DF_REV_4D2) {

usr/src/uts/intel/io/amdzen/amdzen.c

308

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/amdzen.c

961

df->adf_rev = DF_REV_4D2;

usr/src/uts/intel/io/amdzen/zen_umc.c

2185

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/zen_umc.c

2304

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/zen_umc.c

2393

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/zen_umc.c

2460

if ((umc->umc_df_rev >= DF_REV_4D2 &&

usr/src/uts/intel/io/amdzen/zen_umc.c

3563

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/zen_umc.c

3592

case DF_REV_4D2:

usr/src/uts/intel/io/amdzen/zen_umc.c

3919

case DF_REV_4D2:

usr/src/uts/intel/sys/amdzen/df.h

111

#define DF_REV_ALL_4 (DF_REV_4 | DF_REV_4D2)

usr/src/uts/intel/sys/amdzen/df.h

1187

case DF_REV_4D2:

usr/src/uts/intel/sys/amdzen/df.h

337

#define DF_CS_REMAP0A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

340

#define DF_CS_REMAP0B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

343

#define DF_CS_REMAP0C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

346

#define DF_CS_REMAP1A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

349

#define DF_CS_REMAP1B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

352

#define DF_CS_REMAP1C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

355

#define DF_CS_REMAP2A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

358

#define DF_CS_REMAP2B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

361

#define DF_CS_REMAP2C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

364

#define DF_CS_REMAP3A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

367

#define DF_CS_REMAP3B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

370

#define DF_CS_REMAP3C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

590

#define DF_DRAM_BASE_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

600

#define DF_DRAM_LIMIT_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

612

#define DF_DRAM_CTL_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \

usr/src/uts/intel/sys/amdzen/df.h

639

#define DF_DRAM_ILV_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \