usr/src/uts/intel/io/amdzen/amdzen.c

1066

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/amdzen.c

1227

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/amdzen.c

1316

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/amdzen.c

301

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/amdzen.c

940

df->adf_rev = DF_REV_3P5;

usr/src/uts/intel/io/amdzen/zen_umc.c

1693

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/zen_umc.c

2177

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/zen_umc.c

2389

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/zen_umc.c

2423

if (umc->umc_df_rev == DF_REV_3 || umc->umc_df_rev == DF_REV_3P5) {

usr/src/uts/intel/io/amdzen/zen_umc.c

3558

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/zen_umc.c

3588

case DF_REV_3P5:

usr/src/uts/intel/io/amdzen/zen_umc.c

3917

case DF_REV_3P5:

usr/src/uts/intel/sys/amdzen/df.h

1000

#define DF_FIDMASK2_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \

usr/src/uts/intel/sys/amdzen/df.h

109

#define DF_REV_ALL_3 (DF_REV_3 | DF_REV_3P5)

usr/src/uts/intel/sys/amdzen/df.h

1183

case DF_REV_3P5:

usr/src/uts/intel/sys/amdzen/df.h

895

#define DF_SYSCFG_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \

usr/src/uts/intel/sys/amdzen/df.h

980

#define DF_FIDMASK0_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \

usr/src/uts/intel/sys/amdzen/df.h

990

#define DF_FIDMASK1_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \