usr/src/uts/intel/io/vmm/intel/vmx.c

3487

struct pir_desc *pir_desc;

usr/src/uts/intel/io/vmm/intel/vmx.c

3501

struct pir_desc *pir_desc;

usr/src/uts/intel/io/vmm/intel/vmx.c

3507

pir_desc = vlapic_vtx->pir_desc;

usr/src/uts/intel/io/vmm/intel/vmx.c

3527

atomic_store_rel_long(&pir_desc->pending, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

3534

atomic_store_rel_long(&pir_desc->pending, 1);

usr/src/uts/intel/io/vmm/intel/vmx.c

3544

atomic_set_int(&pir_desc->pir[idx], mask);

usr/src/uts/intel/io/vmm/intel/vmx.c

3564

if (atomic_cmpset_long(&pir_desc->pending, 0, 1) != 0) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3669

struct pir_desc *pir_desc;

usr/src/uts/intel/io/vmm/intel/vmx.c

3674

pir_desc = vlapic_vtx->pir_desc;

usr/src/uts/intel/io/vmm/intel/vmx.c

3677

if (atomic_cmpset_long(&pir_desc->pending, 1, 0) == 0) {

usr/src/uts/intel/io/vmm/intel/vmx.c

3686

ASSERT0(pir_desc->pir[0] & 0xffff);

usr/src/uts/intel/io/vmm/intel/vmx.c

3697

atomic_readandclear_int(&pir_desc->pir[i]);

usr/src/uts/intel/io/vmm/intel/vmx.c

3763

vlapic_vtx->pir_desc = &vmx->pir_desc[vcpuid];

usr/src/uts/intel/io/vmm/intel/vmx.c

781

vm_paddr_t pir_desc_pa = vtophys(&vmx->pir_desc[i]);

usr/src/uts/intel/io/vmm/intel/vmx.h

110

CTASSERT(sizeof (struct pir_desc) == 64);

usr/src/uts/intel/io/vmm/intel/vmx.h

134

struct pir_desc pir_desc[VM_MAXCPU];

usr/src/uts/intel/io/vmm/intel/vmx.h

157

CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0);