pf_id
cfg_entry->pf_id = r->func_id;
u16 pf_id)
TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
data->config_table[idx].pf_id = r->func_id;
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
pdev->vars.gen_sp_status_block.sb_data.p_func.pf_id = func;
u8_t pf_id /* The pf id, for multi function mode */;
u8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
u8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
u8 pf_id;
hw->pf_id = (u8)(func_rid & 0xff);
hw->pf_id = (u8)(func_rid & 0x7);
hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
hw->hmc.hmc_fn_id = hw->pf_id;
u8 pf_id;
ctx.pf_num = hw->pf_id;
ctx.pf_num = hw->pf_id;
context.pf_num = hw->pf_id;
reg |= (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
s32 ixgbe_aci_set_pf_context(struct ixgbe_hw *hw, u8 pf_id);
u8 port_id, pf_id, vf_id;
for (pf_id = 0; pf_id < chip_platform->num_pfs; pf_id++) {
ecore_fid_pretend(p_hwfn, p_ptt, (pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT));
offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "pf", pf_id, param_name, param_val);
p_dest->pf_id = p_src->pf_id;
data.pf_id = p_hwfn->rel_pf_id;
u8 pf_id;
u16 num_pfs, pf_id;
for (pf_id = 0; pf_id < num_pfs; pf_id++) {
ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
u8 pf_id = 0;
if (ecore_hw_init_first_eth(p_hwfn, p_ptt, &pf_id) ==
pf_id);
pf_id /= p_hwfn->p_dev->num_ports_in_engine;
NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
u8 pf_id = 0;
if (ecore_hw_init_first_eth(p_hwfn, p_ptt, &pf_id) ==
if (p_hwfn->rel_pf_id == pf_id) {
pf_id);
u8 pf_id;
u16 pf_id)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id, cam_line.cam_line_mapped.camline);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE*pf_id + i*REG_SIZE, *(ram_line_ptr + i));
u16 pf_id,
SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id, cam_line.cam_line_mapped.camline);
cam_line.cam_line_mapped.camline = ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE*pf_id + i*REG_SIZE, *(ram_line_ptr + i));
u8 pf_id,
STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id, (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id << QM_WFQ_VP_PQ_PF_SHIFT));
u8 pf_id,
pq_group = pf_id;
STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
u8 pf_id,
crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET : QM_REG_WFQPFCRD_MSB_RT_OFFSET) + (pf_id % MAX_NUM_PFS_BB);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
u8 pf_id,
STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id, (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
u32 ecore_qm_pf_mem_size(u8 pf_id,
u8 pf_id,
ecore_other_pq_map_rt_init(p_hwfn, port_id, pf_id, num_pf_cids, num_tids, 0);
ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id, max_phys_tcs_per_port, is_first_pf, num_pf_cids, num_vf_cids,
if (ecore_pf_wfq_rt_init(p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port, num_pf_pqs + num_vf_pqs, pq_params))
if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl))
u8 pf_id,
ecore_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
u8 pf_id,
ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
u8 pf_id,
u8 pf_id,
u8 pf_id,
u16 pf_id);
u16 pf_id,
u32 ecore_qm_pf_mem_size(u8 pf_id,
u8 pf_id, u16 vf_number, u8 vf_valid)
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[22].base + ((pf_id) * IRO[22].m1))
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[26].base + ((pf_id) * IRO[26].m1))
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1))
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[33].base + ((pf_id) * IRO[33].m1))
#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[37].base + ((pf_id) * IRO[37].m1))
#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + ((pf_id) * IRO[38].m1))
#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + ((pf_id) * IRO[39].m1))
#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[40].base + ((pf_id) * IRO[40].m1))
#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + ((pf_id) * IRO[41].m1))
#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + ((pf_id) * IRO[42].m1))
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[43].base + ((pf_id) * IRO[43].m1))
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[44].base + ((pf_id) * IRO[44].m1))
#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[47].base + ((pf_id) * IRO[47].m1))
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
u8 pf_id;