pcieadm_regdef_t
static const pcieadm_regdef_t pcieadm_regdef_bridge_membase[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_memlim[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_pfbase[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_pflim[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_header[] = {
static const pcieadm_regdef_t pcieadm_regdef_bist[] = {
static const pcieadm_regdef_t pcieadm_regdef_exprom[] = {
static const pcieadm_regdef_t pcieadm_regdef_pmcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_msictrl[] = {
const pcieadm_cfgspace_print_t *, const pcieadm_regdef_t *,
static const pcieadm_regdef_t pcieadm_regdef_msixctrl[] = {
static const pcieadm_regdef_t pcieadm_regdef_msixtable[] = {
static const pcieadm_regdef_t pcieadm_regdef_msixpba[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devsts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linkcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linkctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linksts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotsts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_rootcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_rootctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_rootsts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devcap2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devctl2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_devsts2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linkcap2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linkctl2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_linksts2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotcap2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotctl2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_slotsts2[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie_caphdr[] = {
static const pcieadm_regdef_t pcieadm_regdef_vpd_addr[] = {
static const pcieadm_regdef_t pcieadm_regdef_sata_cr0[] = {
static const pcieadm_regdef_t pcieadm_regdef_sata_cr1[] = {
static const pcieadm_regdef_t pcieadm_regdef_debug[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_ue[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_ce[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_ctrl[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_rootcom[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_rootsts[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_esi[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_secue[] = {
static const pcieadm_regdef_t pcieadm_regdef_aer_secctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie2_linkctl3[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcie2_linkeq[] = {
static const pcieadm_regdef_t pcieadm_regdef_acs_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_acs_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_l1pm_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_l1pm_ctl1[] = {
static const pcieadm_regdef_t pcieadm_regdef_l1pm_ctl2[] = {
static const pcieadm_regdef_t pcieadm_regdef_l1pm_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_ltr[] = {
static const pcieadm_regdef_t pcieadm_regdef_ari_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ari_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pasid_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_pasid_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_af_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_af_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_af_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_mcast_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_mcast_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_mcast_base[] = {
static const pcieadm_regdef_t pcieadm_regdef_mcast_overlay[] = {
static const pcieadm_regdef_t pcieadm_regdef_vsec[] = {
static const pcieadm_regdef_t pcieadm_regdef_dlf_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_dlf_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_16g_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_16g_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_16g_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_16g_eq[] = {
static const pcieadm_regdef_t pcieadm_regdef_margin_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_margin_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_margin_lane[] = {
static const pcieadm_regdef_t pcieadm_regdef_tph_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_tph_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_tph_st[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_pgsup[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_pgen[] = {
static const pcieadm_regdef_t pcieadm_regdef_sriov_mig[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcix_dev_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcix_dev_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcix_sec_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcix_bridge_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_pcix_bridge_split[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpa_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpa_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpa_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_powbudg_data[] = {
static const pcieadm_regdef_t pcieadm_regdef_powbudg_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ptm_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ptm_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_ats_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ats_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pgreq_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_pgreq_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpc_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpc_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpc_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_dpc_rppio_bits[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_cap1[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_cap2[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_rsrccap[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_rsrcctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_vc_rsrcsts[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_command_pri[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_command_sec[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_linkctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_linkcfg[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_rev[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_linkfreq[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_linkerr[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_linkcap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_feature[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_error[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_memory[] = {
static const pcieadm_regdef_t pcieadm_regdef_ht_msi[] = {
const pcieadm_cfgspace_print_t *print, const pcieadm_regdef_t *regdef,
static const pcieadm_regdef_t pcieadm_regdef_rcld_desc[] = {
static const pcieadm_regdef_t pcieadm_regdef_rcld_link[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_rxts1[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_rxts2[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_txts1[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_txts2[] = {
static const pcieadm_regdef_t pcieadm_regdef_32g_eq[] = {
static const pcieadm_regdef_t pcieadm_regdef_npem_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_npem_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_npem_sts[] = {
static const pcieadm_regdef_t pcieadm_regdef_ap_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_ap_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_ap_data1[] = {
static const pcieadm_regdef_t pcieadm_regdef_ap_data2[] = {
static const pcieadm_regdef_t pcieadm_regdef_ap_sen[] = {
static const pcieadm_regdef_t pcieadm_regdef_rcecea_bus[] = {
const pcieadm_cfgspace_print_t *print, const pcieadm_regdef_t *regdef,
static const pcieadm_regdef_t pcieadm_regdef_rtr1[] = {
static const pcieadm_regdef_t pcieadm_regdef_rtr2[] = {
static const pcieadm_regdef_t pcieadm_regdef_doe_cap[] = {
static const pcieadm_regdef_t pcieadm_regdef_doe_ctl[] = {
static const pcieadm_regdef_t pcieadm_regdef_doe_sts[] = {
const pcieadm_regdef_t *regdef = arg;
static const pcieadm_regdef_t pcieadm_regdef_command[] = {
static const pcieadm_regdef_t pcieadm_regdef_status[] = {
static const pcieadm_regdef_t pcieadm_regdef_class[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_iobase[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridge_iolim[] = {
static const pcieadm_regdef_t pcieadm_regdef_bridgests[] = {