pcieadm_cap_info_vers
return (pcieadm_cap_info_vers(walkp, cap, off, versp, lenp, subcap));
{ PCI_CAP_ID_FLR, "af", "Advanced Features", pcieadm_cap_info_vers,
{ PCIE_EXT_CAP_ID_VC, "vc", "Virtual Channel", pcieadm_cap_info_vers,
{ PCIE_EXT_CAP_ID_SER, "sn", "Serial Number", pcieadm_cap_info_vers,
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_powbudg } } },
"Root Complex Link Declaration", pcieadm_cap_info_vers,
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_rcecea_v1 },
pcieadm_cap_info_vers, { { 0x1, 0x1c, pcieadm_cap_vc } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_vsec } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_acs } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_ari } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_ats } } },
pcieadm_cap_info_vers, { { 1, 0x40, pcieadm_cap_sriov } } },
pcieadm_cap_info_vers, { { 1, 0x30, pcieadm_cap_mcast } } },
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_pgreq } } },
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_dpa } } },
pcieadm_cap_info_vers, { { 1, 0xc, pcieadm_cap_tph } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_ltr } } },
pcieadm_cap_info_vers, { { 1, 0xc, pcieadm_cap_pcie2 } } },
pcieadm_cap_info_vers, { { 1, 0x8, pcieadm_cap_pasid } } },
pcieadm_cap_info_vers, { { 1, 0x30, pcieadm_cap_dpc } } },
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_l1pm_v1 },
pcieadm_cap_info_vers, { { 1, 0xc, pcieadm_cap_info_ptm } } },
pcieadm_cap_info_vers, { { 1, 0xc, pcieadm_cap_rtr } } },
pcieadm_cap_info_vers, { { 1, 0xc, pcieadm_cap_dlf } } },
pcieadm_cap_info_vers, { { 1, 0x22, pcieadm_cap_16g } } },
"Lane Margining at the Receiver", pcieadm_cap_info_vers,
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_npem } } },
pcieadm_cap_info_vers, { { 1, 0x24, pcieadm_cap_32g } } },
pcieadm_cap_info_vers, { { 1, 0x14, pcieadm_cap_ap } } },
pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_doe },