pbm_err
pbm_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err)
pbm_err->pbm_bridge_type, pbm_err->pbm_err_class);
PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat,
PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm,
PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat,
PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr,
PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar,
PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl,
PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log,
pbm_errstate_t pbm_err;
pci_pbm_errstate_get(pci_p, &pbm_err);
prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr);
secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr);
(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) {
(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) {
ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err);
ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr);
pbm_ctl_stat = pbm_err.pbm_ctl_stat;
pci_cfg_stat = pbm_err.pbm_pci.pci_cfg_stat;
pbm_err.pbm_pci.pci_err_class = PCI_REC_SERR;
PCI_ERROR_SUBCLASS, pbm_err.pbm_pci.pci_err_class);
pbm_err.pbm_pci.pci_cfg_comm, PCI_PA,
pbm_err.pbm_err_class = PCI_PSY_SBH;
pbm_ereport_post(dip, derr->fme_ena, &pbm_err);
pci_clear_error(pci_p, &pbm_err);
uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK;
uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK;
pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr);
pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr);
pbm_err_p->pbm_err = e;
pbm_err_p->pbm_err = e;
pbm_errstate_t pbm_err;
pci_pbm_errstate_get(pci_p, &pbm_err);
prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr);
secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr);
(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) {
pcix_ma_behind_bridge(&pbm_err)) {
(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) {
ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err);
if ((ret = pcix_log_pbm(pci_p, derr->fme_ena, &pbm_err))
if ((ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr))
if ((pbm_err.pbm_ctl_stat & pci_pbm_err_tbl[i].pbm_reg_bit) &&
pbm_err.pbm_err_class =
pbm_ereport_post(dip, derr->fme_ena, &pbm_err);
pbm_err.pbm_bridge_type,
if ((pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) &&
pbm_err.pbm_err_class = PCI_SCH_SBH;
pbm_ereport_post(dip, derr->fme_ena, &pbm_err);
if (pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SERR) {
pbm_err.pbm_pci.pci_cfg_stat, PCI_CONFIG_COMMAND,
DATA_TYPE_UINT16, pbm_err.pbm_pci.pci_cfg_comm,
if (pbm_err.pbm_ctl_stat & TOMATILLO_PCI_CTRL_PCI_DTO_ERR) {
pbm_err.pbm_pci.pci_cfg_stat,
pbm_err.pbm_pci.pci_cfg_comm,
if ((pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_PERROR) &&
!(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_S_SYSERR)) {
if (pbm_err.pbm_va_log) {
derr->fme_ena, (void *)&pbm_err.pbm_va_log);
if (pbm_err.pbm_ctl_stat & SCHIZO_PCI_CTRL_PCI_MMU_ERR) {
if (iommu_err_handler(dip, derr->fme_ena, &pbm_err)
pci_clear_error(pci_p, &pbm_err);
iommu_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err)
pbm_err->pbm_bridge_type, pbm_err->pbm_err_class);
PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat,
PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm,
PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat,
PCI_PBM_IOMMU_CTRL, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_stat,
PCI_PBM_IOMMU_TFAR, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_tfar,
PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl,
PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log,
pcix_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err)
pbm_err->pbm_bridge_type, pbm_err->pbm_err_class);
PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat,
PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm,
PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat,
PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr,
PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar,
PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl,
PCIX_STAT, DATA_TYPE_UINT64, pbm_err->pbm_pcix_stat,
PCIX_PFAR, DATA_TYPE_UINT32, pbm_err->pbm_pcix_pfar,
*pcbm_p->pcbm_async_flt_status_reg = pbm_err;
pcmu_pbm_errstate_t pbm_err;
pcmu_pbm_errstate_get(pcmu_p, &pbm_err);
prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr);
secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr);
(pbm_err.pcbm_pci.pcmu_cfg_stat & PCI_STAT_R_MAST_AB)) {
ret = pcmu_pbm_afsr_report(dip, derr->fme_ena, &pbm_err);
ret = pcmu_cfg_report(dip, derr, &pbm_err.pcbm_pci, caller, prierr);
pcmu_clear_error(pcmu_p, &pbm_err);
pcmu_pbm_errstate_t *pbm_err)
prierr = PBM_AFSR_TO_PRIERR(pbm_err->pbm_afsr);
secerr = PBM_AFSR_TO_SECERR(pbm_err->pbm_afsr);
PCI_PBM_AFAR, pbm_err->pbm_afar,
PCI_PBM_AFSR, pbm_err->pbm_afsr,
PCI_PBM_CSR, pbm_err->pbm_ctl_stat,
pcmu_pbm_errstate_t *pbm_err);
pcmu_pbm_errstate_t *pbm_err);
uint32_t pbm_err;
uint32_t pbm_err;
pbm_errstate_t *pbm_err);