pci_config_put8
pci_config_put8(pci, PCI_LATTMR, 0x40);
pci_config_put8(pci, PCI_TRDYTO, 0);
pci_config_put8(pci, PCI_RETRIES, 0);
pci_config_put8(pci, PCI_LATTMR, 0x40);
pci_config_put8(pci, PCI_TRDYTO, 0);
pci_config_put8(pci, PCI_RETRIES, 0);
pci_config_put8(pci, PCI_MINGNT, 0);
pci_config_put8(pci, PCI_MAXLAT, 0);
pci_config_put8(sc->sc_cfg_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(sc->sc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8);
pci_config_put8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(asc->asc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, M1575_PCIACD_REG, 4);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, M1575_PCIACD_REG, 2);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, M1575_PCIACD_REG, 4);
pci_config_put8(pcih, M1575_PCIACD_REG, 0);
pci_config_put8(pcih, PCI_CONF_LATENCY_TIMER,
pci_config_put8(statep->hda_pci_handle,
pci_config_put8(statep->hda_pci_handle, AUDIOHD_ATI_PCI_MISC2,
pci_config_put8(statep->hda_pci_handle, AUDIOHD_CORB_SIZE_OFF,
pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(bgep->cfg_handle, regno, regval);
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(handle, PCI_BCNF_SECBUS, bus_range->lo);
pci_config_put8(handle, PCI_BCNF_SUBBUS, bus_range->hi);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus);
pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW,
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO,
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(handle, PCI_CONF_ILINE, intline);
pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary);
pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary);
pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF);
pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */
pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */
pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */
pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0);
pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0);
pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0);
pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(qlt->pcicfg_acc_handle,
pci_config_put8(sc->pci_regh, reg, val);
pci_config_put8(Adapter->osdep.cfg_handle,
pci_config_put8(ha->pci_handle, off, val);
pci_config_put8(hmep->pci_config_handle,
pci_config_put8(config_handle, slotinfop->hs_csr_location, *hs_csr);
pci_config_put8(sc->sc_pcih, 0x41, 0);
pci_config_put8(handle, mgp->vso + 0x10, 0x3);
pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(ngep->cfg_handle, regno, regval);
pci_config_put8(conf_handle,
pci_config_put8(h, offset, data);
pci_config_put8(bus_p->bus_cfg_hdl, off, val);
pci_config_put8(bus_p->bus_cfg_hdl,
pci_config_put8(bus_p->bus_cfg_hdl,
pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ,
pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER,
pci_config_put8(qede->pci_cfg_handle, addr,
pci_config_put8(rgep->cfg_handle, regno, regval);
pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);
pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(cfgh, where, val)
pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ,
pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER,
pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value);
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTCTRL,
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_GBLACT, 0);
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTLOW, throttle);
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTCTRL,
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTCTRL,
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_GBLACT,
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTLOW,
pci_config_put8(fipe_mc_ctrl.mc_pci_hdl, FIPE_MC_THRTCTRL,
pci_config_put8(cfg_handle,
pci_config_put8(hdl, (off_t)reg, (uint8_t)val);
pci_config_put8(cfg_handle,
pci_config_put8(stub->azns_cfgspace, reg, val);
#define AMR_QCLEAR_INTR(sc) pci_config_put8(sc->regsmap_handle, \
#define AMR_QENABLE_INTR(sc) pci_config_put8(sc->regsmap_handle, \
#define AMR_QDISABLE_INTR(sc) pci_config_put8(sc->regsmap_handle, \
#define AMR_SPUT_ISTAT(sc, val) pci_config_put8(sc->regsmap_handle, \
#define AMR_SACK_INTERRUPT(sc) pci_config_put8(sc->regsmap_handle, \
#define AMR_SPOST_COMMAND(sc) pci_config_put8(sc->regsmap_handle, AMR_SCMD, \
pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \
pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \
#define AMR_SBYTE_SET(sc, reg, val) pci_config_put8(sc->regsmap_handle, \
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary);
pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary);
pci_config_put8(config_handle, PCI_BCNF_SUBBUS, subordinate);
pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus);
pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW,
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(h, PCI_BCNF_IO_BASE_LOW,
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(h, PCI_CONF_ILINE, 0xf);
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0);
pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 0xff);
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(cfg_hdl, reg->offset,
pci_config_put8(acb->pci_acc_handle, 0x84, 0x20);
pci_config_put8(acb->pci_acc_handle, i, value[i]);
pci_config_put8(cfg, cio.pci_off, cio.pci_data);
pci_config_put8(erip->pci_config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(conf_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(conf_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary);
pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary);
pci_config_put8(config_handle, PCI_BCNF_SUBBUS, subordinate);
pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus);
pci_config_put8(handle, PCI_BCNF_PRIBUS, (uint_t)pbus);
pci_config_put8(handle, PCI_BCNF_SECBUS, (uint_t)sbus);
pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW,
pci_config_put8(handle, PCI_CONF_ILINE, 0xf);
pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(h, PCI_CONF_ILINE, 0xf);
pci_config_put8(h, PCI_BCNF_IO_BASE_LOW,
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(h, PCI_CONF_ILINE, 0xf);
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0);
pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 0xff);
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW,
pci_config_put8(isa_handle, 0x58, val & 0xFB);
pci_config_put8(isa_handle, 0x58, val);
pci_config_put8(isa_handle, 0x58, val & 0xF7);
pci_config_put8(isa_handle, 0x58, val);
pci_config_put8(platform_isa_handle, 0x58, val & 0xFB);
pci_config_put8(platform_isa_handle, 0x58, val);
pci_config_put8(platform_isa_handle, 0x58, val & 0xF7);
pci_config_put8(platform_isa_handle, 0x58, val);
pci_config_put8(grover_isa_handle, 0x58, val & 0xFB);
pci_config_put8(grover_isa_handle, 0x58, val);
pci_config_put8(grover_isa_handle, 0x58, val & 0xF7);
pci_config_put8(grover_isa_handle, 0x58, val);
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(ch, PCI_BCNF_PRIBUS,
pci_config_put8(ch, PCI_BCNF_SECBUS,
pci_config_put8(ch, PCI_BCNF_SUBBUS,
pci_config_put8(ch, PCI_CONF_CACHE_LINESZ,
pci_config_put8(ch, PCI_CONF_LATENCY_TIMER,
pci_config_put8(ch, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
pci_config_put8(softsp->pmubus_reghdl, offset, tmp);
pci_config_put8(softsp->pmubus_reghdl, offset, value);
pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
pci_config_put8(isa_handle, 0x58, val & 0xFB);
pci_config_put8(isa_handle, 0x58, val);
pci_config_put8(isa_handle, 0x58, val & 0xF7);
pci_config_put8(isa_handle, 0x58, val);
pci_config_put8(isa_handle, IDEIC_RINDEX, val & 0xFB);
pci_config_put8(isa_handle, IDEIC_RINDEX, val);
pci_config_put8(isa_handle, IDEIC_RINDEX, val & 0xF7);
pci_config_put8(isa_handle, IDEIC_RINDEX, val);
pci_config_put8(isa_handle, 0x58, val & 0xFB);
pci_config_put8(isa_handle, 0x58, val);
pci_config_put8(isa_handle, 0x58, val & 0xF7);
pci_config_put8(isa_handle, 0x58, val);